CAT93C66 Datasheet, PDF (5/17 Pages) ON Semiconductor – 4-Kb Microwire Serial CMOS EEPROM

CAT93C66
POWER-UP TIMING^{(1) (2)}
Symbol Parameter
Max
Units
t_PUR
Power-up to Read Operation
t_PUW
Power-up to Write Operation
1
ms
1
ms
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤ ^{50 ns}
0.4V to 2.4V
4.5V ≤ V_CC ≤ 5.5V
0.8V, 2.0V
4.5V ≤ V_CC ≤ 5.5V
0.2V_CC to 0.7V_CC 1.8V ≤ V_CC ≤ 4.5V
0.5V_CC
1.8V ≤ V_CC ≤ 4.5V
Current Source I_OLmax/I_OHmax; CL=100pF
DEVICE OPERATION
The CAT93C66 is a 4096-bit nonvolatile memory
intended for use with industry standard micropro–
cessors. The CAT93C66 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 11-bit instructions control the reading, writing and
erase operations of the device. When organized as X8,
seven 12-bit instructions control the reading, writing and
erase operations of the device. The CAT93C66 operates
on a single power supply and will generate on chip, the
high voltage required during any write operation.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The serial communication protocol follows the timing
shown in Figure 1.
The ready/busy status can be determined after the start
of internal write cycle by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state
on the rising edge of the clock (SK). Placing the DO pin
into the high impedance state is recommended in
applications where the DI pin and the DO pin are to be
tied together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2-bit (or 4-bit) opcode, 8-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations). The instruction format is shown in
Instruction Set table.
INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start
Bit
1
1
1
1
1
1
1
Opcode
10
11
01
00
00
00
00
Address
x8
x16
A8-A0
A7-A0
A8-A0
A7-A0
A8-A0
A7-A0
11XXXXXXX 11XXXXXX
00XXXXXXX 00XXXXXX
10XXXXXXX 10XXXXXX
01XXXXXXX 01XXXXXX
Data
x8
x16
D7-D0 D15-D0
D7-D0 D15-D0
Comments
Read Address AN – A0
Clear Address AN – A0
Write Address AN – A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
© 2009 SCILLC. All rights reserved
5
Characteristics subject to change without notice
Doc. No. MD-1089 Rev. T