CAT25512YI-GT3 Datasheet, PDF (7/16 Pages) ON Semiconductor – 512-Kb SPI Serial CMOS EEPROM

CAT25512
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and a data byte as shown in Figure 5. Internal programming
will start after the low to high CS transition. During an
internal write cycle, all commands, except for RDSR (Read
Status Register) will be ignored. The RDY bit will indicate
if the internal write cycle is in progress (RDY high), or the
device is ready to accept commands (RDY low).
Page Write
After sending the first data byte to the CAT25512, the host
may continue sending data, up to a total of 128 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT25512 is
automatically returned to the write disable state.
Write Identification Page
The additional 128−byte Identification Page (IP) can be
written with user data using the same Write commands
sequence as used for Page Write to the main memory array
(Figure 6). The IPL bit from the Status Register must be set
(IPL = 1) using the WRSR instruction, before attempting
to write to the IP.
The address bits [A15:A7] are Don’t Care and the
[A6:A0] bits define the byte address within the
Identification Page. In addition, the Byte Address must point
to a location outside the protected area defined by the BP1,
BP0 bits from the Status Register. When the full memory
array is write protected (BP1, BP0 = 1,1), the write
instruction to the IP is not accepted and not executed.
Also, the write to the IP is not accepted if the LIP bit from
the Status Register is set to 1 (the page is locked in
Read−only mode).
Table 11. BYTE ADDRESS
Device
Main Memory Array
Identification Page
Address Significant Bits
A15 − A0
A6 − A0
# Address Clock Pulses
16
16
CS
SCK
SI
012345678
21 22 23 24 25 26 27 28 29 30 31
00
OPCODE
00 0 01
BYTE ADDRESS*
DATA IN
0 A_N
A₀ D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
Figure 5. Byte WRITE Timing
CS
SCK
012345678
21 22 23 24−31 32−39 ^{24+(N−1)x8−1 .. 24+(N−1)x8}
24+Nx8−1
OPCODE
BYTE ADDRESS*
DATA IN
Data Byte N
SI
0 0 0 0 0 0 1 0 AN
A₀
7..1 0
Data Data Data
Byte 1 Byte 2 Byte 3
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
Figure 6. Page WRITE Timing
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