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CAT25512YI-GT3 Datasheet, PDF (3/16 Pages) ON Semiconductor – 512-Kb SPI Serial CMOS EEPROM
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CAT25512
Table 4. PIN CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V) (Note 2)
Symbol
Test
Conditions
COUT
CIN
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
VOUT = 0 V
VIN = 0 V
Min
Typ
Max
Units
8
pF
8
pF
Table 5. A.C. CHARACTERISTICS (TA = −40°C to +125°C, unless otherwise specified.) (Note 5)
VCC = 1.8 V − 5.5 V
−405C to +855C
VCC = 2.5 V − 5.5 V
−405C to +1255C
VCC = 4.5 V − 5.5 V
−405C to +855C
Symbol
Parameter
Min
Max
Min
Max
Min
fSCK
Clock Frequency
DC
5
DC
10
DC
tSU
Data Setup Time
20
10
5
tH
Data Hold Time
20
10
5
tWH
SCK High Time
75
40
20
tWL
SCK Low Time
75
40
20
tLZ
HOLD to Output Low Z
50
25
tRI (Note 6)
Input Rise Time
2
2
tFI (Note 6)
Input Fall Time
2
2
tHD
HOLD Setup Time
0
0
0
tCD
HOLD Hold Time
10
10
5
tV
Output Valid from Clock Low
75
40
tHO
Output Hold Time
0
0
0
tDIS
Output Disable Time
50
20
tHZ
HOLD to Output High Z
100
25
tCS
CS High Time
80
40
20
tCSS
CS Setup Time
60
30
15
tCSH
CS Hold Time
60
30
15
tCNS
CS Inactive Setup Time
60
30
15
tCNH
CS Inactive Hold Time
60
30
15
tWPS
WP Setup Time
10
10
10
tWPH
WP Hold Time
10
10
10
tWC (Note 7) Write Cycle Time
5
5
5. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 30 pF
6. This parameter is tested initially and after a design or process change that affects the parameter.
7. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Max
20
25
2
2
20
20
25
5
Table 6. POWER−UP TIMING (Notes 6, 8)
Symbol
Parameter
Max
tPUR
Power−up to Read Operation
1
tPUW
Power−up to Write Operation
1
8. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Units
ms
ms
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