CAT25010_12 Datasheet, PDF (7/18 Pages) ON Semiconductor – 1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM

CAT25010, CAT25020, CAT25040
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 8−bit address
and data as shown in Figure 5. For the CAT25040, bit 3 of
the write instruction opcode contains A8 address bit.
Internal programming will start after the low to high CS
transition. During an internal write cycle, all commands,
except for RDSR (Read Status Register) will be ignored.
The RDY bit will indicate if the internal write cycle is in
progress (RDY high), or the device is ready to accept
commands (RDY low).
Page Write
After sending the first data byte to the CAT25010/20/40,
the host may continue sending data, up to a total of 16 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the
CAT25010/20/40 is automatically returned to the write
disable state.
CS
SCK
SI
012345678
13 14 15 16 17 18 19 20 21 22 23
00
OPCODE
0 0 X* 0 1
BYTE ADDRESS
DATA IN
0 A₇
A₀ D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
Figure 5. Byte WRITE Timing
CS
SCK
012345678
13 14 15 16−23 24−31 ^{16+(N−1)x8−1..16+(N−1)x8}
16+Nx8−1
OPCODE
BYTEADDRESS
DATA IN
SI
0 0 0 0 X* 0 1 0 A7
A₀
Data Data Data
Byte 1 Byte 2 Byte 3
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
Figure 6. Page WRITE Timing
Data Byte N
7..1 0
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