ASM2I9940L Datasheet, PDF (7/10 Pages) Alliance Semiconductor Corporation – Low Voltage 1:18 Clock Distribution Chip

PECL_CLK
PECL_CLK
ASM2I9940L
VPP
Q
tPD
VCMR
VCC
VCC ÷2
GND
Figure 5. Propagation Delay (t_PD) Test Reference
LVCMOS_CLK
VCC
VCC ÷2
GND
Q
tPD
VCC
VCC ÷2
GND
Figure 6. LVCMOS Propagation Delay (t_PD) Test Reference
VCC
VCC ÷2
GND
tP
T0
DC (tP ÷T0 Χ 100%)
The time from the PLL controlled edge to the
non-controlled edge, divided by the time
between PLL controlled edges, expressed as a
percentage.
Figure 7. Output Duty Cycle (DC)
VCC
VCC ÷2
GND
tSK(O)
VOH
VCC ÷2
GND
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 8. Output–to–Output Skew t_SK(O)
VCC = 3.3V V CC = 2.5V
2.4
1.8V
0.55
0.6V
tF
tR
Figure 9. Output Transition Time Test Reference
VCC = 3.3V VCC = 2.5V
2.0
1.7V
0.8
0.7V
tF
tR
Figure 10. Input Transition Time Test Reference
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