AND8391-D Datasheet, PDF (7/8 Pages) ON Semiconductor – Thermal Considerations for the ON Semiconductor

AND8391/D
The device and heat sink will require analysis for worst
case condition to account for 100% duty cycle.
Figures 15 and 16 will assist to determine the temperature
rise caused by a power pulse.
Example: If the control input is a 500 Hz, 20% duty cycle
pwm applied to the three red LED circuit of Figure 11, the
1000
100
10
50% Duty Cycle
20%
10%
5%
2%
1%
1
Single Pulse
R(t) for 300 mm² of 1 oz Cu for a SOD−123 from Figure 15
would be [ 90°C/W. Therefore; 216 mW x 90°C/W =
19.4°C temperature rise.
0.1
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
PULSE TIME (s)
Figure 15. SOD−123 NSI45030T1G PCB Cu Area 300 mm² PCB Cu thk 1.0 oz
1000
1000
5%
100
20%
10%
10
50% Duty Cycle
1%
2%
1 Single Pulse
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
PULSE TIME (s)
Figure 16. CCR SOT−223 NSI45030ZT1G PCB Cu Area 300 mm² PCB Cu thk 2.0 oz
Summary:
The thermal behavior of a CCR is generalized in the
following matrix:
I_reg(SS)
T_J
T_A ↑
↓
↑
Heatsink Area ↑
↑
↓
Vak ↑
NC*
↑
*In general SOD−123 for 3 V < Vak < 10 V, all other variables con-
stant: I_reg(SS) changes < 2 mA (less @ T_A > 25°C).
In general SOT−223 for 3 V < Vak < 10 V, all other variables con-
stant: I_reg(SS) changes < 3 mA.
Figure 17.
1000
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