MT9F002 Datasheet, PDF (65/93 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor
Sensor Core Digital Data Path
Sensor Core Digital Data Path
Test Patterns
The MT9F002 supports a number of test patterns to facilitate system debug. Test
patterns are enabled using test_pattern_mode (R0x0600–1). The test patterns are listed
in Table 20.
Table 20: Test Patterns
HiSPi Test Patterns
test_pattern_mode
0
1
2
3
4
256
257
258
Description
Normal operation: no test pattern
Solid color
100% color bars
Fade-to-gray color bars
PN9 link integrity pattern (only on sensors with serial
interface)
Walking 1s (12-bit value)
Walking 1s (10-bit value)
Walking 1s (8-bit value)
Test patterns 0–3 replace pixel data in the output image (the embedded data rows are
still present). Test pattern 4 replaces all data in the output image (the embedded data
rows are omitted and test pattern data replaces the pixel data).
Test patterns specific to the HiSPi are also generated. The test patterns are enabled by
using test_enable (R0x31C6 - 7) and controlled by test_mode (R0x31C6[6:4]).
Table 21: HiSPi Test Patterns
test_mode
0
1
2
3
4
5
Description
Transmit a constant 0 on all enabled data lanes.
Transmit a constant 1 on all enabled data lanes.
Transmit a square wave at half the serial data rate on all enabled data lanes.
Transmit a square wave at the pixel rate on all enabled data lanes.
Transmit a continuous sequence of pseudo random data, with no SAV code, copied on all enabled data
lanes.
Replace data from the sensor with a known sequence copied on all enabled data lanes.
For all of the test patterns, the MT9F002 registers must be set appropriately to control
the frame rate and output timing. This includes:
• All clock divisors
• x_addr_start
• x_addr_end
• y_addr_start
• y_addr_end
• frame_length_lines
• line_length_pck
• x_output_size
• y_output_size
MT9F002 DS Rev. H Pub. 6/15 EN
65
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