PCA9617A Datasheet, PDF (6/15 Pages) NXP Semiconductors – Level translating Fm+ I2C-bus repeater

PCA9617A
Figure 5. Bus A (0.9 V to 5.5 V Bus) Waveform
The internal comparator requires that 0.4 x V_CC(A) be less
than or equal to V_CC(B) – 0.8 V for the device to operate.
Since A port is 5 V tolerant, the V_CC(A) can be lowered to
support device spectrum while still supporting 5 V signals
on the A port.
On the B bus side of the PCA9617A, the clock and data
lines would have a positive offset from ground equal to the
V_OL of the PCA9617A. After the eighth clock pulse, the data
line will be pulled to the V_OL of the slave device which is
very close to ground in this example. At the end of the
acknowledge, the level rises only to the LOW level set by the
driver in the PCA9617A for a short delay while the A bus
side rises above 0.3 V_CC(A) then it continues HIGH. It is
important to note that any arbitration or clock stretching
events require that the LOW level on the B bus side at the
input of the PCA9617A (V_IL) be at or below 0.4 V to be
recognized by the PCA9617A and then transmitted to the A
bus side.
Multiple PCA9617A port A sides can be connected in a
star configuration (Figure 6), allowing all nodes to
communicate with each other.
Figure 6. Typical Star Application
Multiple PCA9617As can be connected in series
(Figure 7) as long as port A is connected to port B. I²C−bus
slave devices can be connected to any of the bus segments.
The number of devices that can be connected in series is
limited by repeater delay/time−of−flight considerations on
the maximum bus speed requirements.
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