MC74HC164A_06 Datasheet, PDF (6/11 Pages) ON Semiconductor – 8−Bit Serial−Input/Parallel−Output Shift Register

MC74HC164A
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 1, 2)
Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A1 and
A2 inputs must be high, thereby allowing one input to be
used as a data−enable input. When only one serial input is
used, the other must be connected to V_CC.
Clock (Pin 8)
Shift Register Clock. A positive−going transition on this
pin shifts the data at each stage to the next stage. The shift
register is completely static, allowing clock rates down to
DC in a continuous or intermittent mode.
OUTPUTS
Q_A − Q_H (Pins 3, 4, 5, 6, 10, 11, 12, 13)
Parallel Shift Register Outputs. The shifted data is
presented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)
Active−Low, Asynchronous Reset Input. A low voltage
applied to this input resets all internal flip−flops and sets
Outputs Q_A − Q_H to the low level state.
SWITCHING WAVEFORMS
t_r
t_f
90%
V_CC
CLOCK
50%
10%
GND
t_w
90%
Q 50%
10%
1/f_max
t_PLH
t_PHL
t_TLH
t_THL
t_w
RESET
50%
V_CC
GND
t_PHL
Q
50%
CLOCK
t_rec
V_CC
50%
GND
Figure 1.
Figure 2.
VALID
V_CC
A1 OR A2
50%
GND
t_su
t_h
V_CC
CLOCK
50%
GND
Figure 3.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
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