KAC-06040 Datasheet, PDF (6/43 Pages) ON Semiconductor – ESD6100

KAC−06040
Table 6. LVDS PIN DESCRIPTION
Pin
Name
Description
E01 1DCLK+
Bank 1
E02 1DCLK− ^{LVDS Clock}
D01 1DATA0+
D02 1DATA0−
C01 1DATA1+
C02 1DATA1−
B01 1DATA2+
B02 1DATA2−
Bank 1
A03 1DATA3+
LVDS Data
B03 1DATA3−
A04 1DATA4+
B04 1DATA4−
A05 1DATA5+
B05 1DATA5−
A06 1DATA6+
B06 1DATA6−
Pin
Name
Description
C07 3DCLK+
Bank 3
C08 3DCLK− ^{LVDS Clock}
A07 3DATA0+
B07 3DATA0−
A08 3DATA1+
B08 3DATA1−
A09 3DATA2+
B09 3DATA2−
Bank 3
A10 3DATA3+
LVDS Data
B10 3DATA3−
A11 3DATA4+
B11 3DATA4−
A12 3DATA5+
B12 3DATA5−
A13 3DATA6+
B13 3DATA6−
Pin
Name
Description
C15 5DCLK+
Bank 5
C16 5DCLK− ^{LVDS Clock}
A15 5DATA0+
B15 5DATA0−
A16 5DATA1+
B16 5DATA1−
A17 5DATA2+
B17 5DATA2−
A18 5DATA3+
B18 5DATA3−
Bank 5
LVDS Data
A19 5DATA4+
B19 5DATA4−
A20 5DATA5+
B20 5DATA5−
A21 5DATA6+
B21 5DATA6−
Pin
Name
Description
A22 7DCLK+
Bank 7
B22 7DCLK− ^{LVDS Clock}
A23 7DATA0+
B23 7DATA0−
A24 7DATA1+
B24 7DATA1−
A25 7DATA2+
B25 7DATA2−
Bank 7
B27 7DATA3+
LVDS Data
B26 7DATA3−
C27 7DATA4+
C26 7DATA4−
D27 7DATA5+
D26 7DATA5−
E27 7DATA6+
E26 7DATA6−
Pin
AA01
AA02
AB01
AB02
AC01
AC02
AD01
AD02
AE03
AD03
AE04
AD04
AE05
AD05
AE06
AD06
Name
0DCLK+
0DCLK−
0DATA0+
0DATA0−
0DATA1+
0DATA1−
0DATA2+
0DATA2−
0DATA3+
0DATA3−
0DATA4+
0DATA4−
0DATA5+
0DATA5−
0DATA6+
0DATA6−
Description
Bank 0
LVDS Clock
Bank 0
LVDS Data
Pin
AC07
AC08
AE07
AD07
AE08
AD08
AE09
AD09
AE10
AD10
AE11
AD11
AE12
AD12
AE13
AD13
Name
2DCLK+
2DCLK−
2DATA0+
2DATA0−
2DATA1+
2DATA1−
2DATA2+
2DATA2−
2DATA3+
2DATA3−
2DATA4+
2DATA4−
2DATA5+
2DATA5−
2DATA6+
2DATA6−
Description
Bank 2
LVDS Clock
Bank 2
LVDS Data
Pin
AC15
AC16
AE15
AD15
AE16
AD16
AE17
AD17
AE18
AD18
AE19
AD19
AE20
AD20
AE21
AD21
Name
4DCLK+
4DCLK−
4DATA0+
4DATA0−
4DATA1+
4DATA1−
4DATA2+
4DATA2−
4DATA3+
4DATA3−
4DATA4+
4DATA4−
4DATA5+
4DATA5−
4DATA6+
4DATA6−
Description
Bank 4
LVDS Clock
Bank 4
LVDS Data
Pin
AE22
AD22
AE23
AD23
AE24
AD24
AE25
AD25
AD26
AD27
AC26
AC27
AB26
AB27
AA26
AA27
Name
6DCLK+
6DCLK−
6DATA0+
6DATA0−
6DATA1+
6DATA1−
6DATA2+
6DATA2−
6DATA3+
6DATA3−
6DATA4+
6DATA4−
6DATA5+
6DATA5−
6DATA6+
6DATA6−
Description
Bank 6
LVDS Clock
Bank 6
LVDS Data
1. All LVDS Data and Clock lines must be routed with 100 W differential transmission line traces.
2. All the traces for a single LVDS Bank should be the same physical length to minimize skew between the clock and data lines.
3. In 2 Bank mode, only LVDS banks 0 and 1 are active.
4. In 4 Bank mode, only LVDS bank 0, 1, 2, and 3 are active.
5. Float the pins of unused LVDS Banks to conserve power.
6. Unused pins in active banks (due to ADC bit depth < 14) are automatically tri-stated to save power, but these can also be floated.
www.onsemi.com
6