JLC1562BE Datasheet, PDF (6/9 Pages) ON Semiconductor – I2C Bus I/O Expander

JLC1562B
READ WRITE DATA FORMAT
<<READ MODE>>
S 0 1 1 1 A2 A1 A0 1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK P
Slave Address
Read Data
Slave Address
A0 − A2
I/O Expander Device Address (Pins A0 − A2)
A3 − A6
A6 A5 A4 A3 is hard wired as 0 1 1 1
R/W
1 : READ ADDRESS
Read Data
D5 − D7
D0 − D4
Output of Comparator “A”. (V_th = 1/2 V_DD)
Output of Comparator “B”. (V_th = 1/2 V_DD OR V_DAC)
READ LATCH Bit Controls when Data Will Be Latched.
<<WRITE MODE>>
S 0 1 1 1 A2 A1 A0 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK P
Slave Address
Write Data (1)
Write Data (2)
Slave Address
A0 − A2
A3 − A6
R/W
I/O Expander Device Address (Pins A0 − A2)
A6 A5 A4 A3 is hard wired as 0 1 1 1
0 : WRITE ADDRESS
Write Data (1)
Write Data (2)
D0 − D7
D7
D6
D0 − D5
Device Pins P0 to P7 Output Bits.
READ LATCH CONTROL
Latch Control of Signals C0 − C4
in the Device BLOCK DIAGRAM
0 : Data is latched at the ACK after a READ COMMAND.
1 : Data is latched when Comparator “B” switches from 0 to 1.
(switch point is controlled by V_th.)
1 : Data is reset at the ACK after a READ COMMAND.
COMPARATOR “B” V_ref Control Bit
0
:
Vref
+
40
80
VDD
1 : Vref + VDAC
DAC Input Bits
http://onsemi.com
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