CS4192_05 Datasheet, PDF (6/8 Pages) ON Semiconductor – Single Air−Core Gauge Driver

CS4192
270°
V_SIN−
V_COS+
360/0°
0.748 V_BB
q
IV
I
0.748 V_BB 0.748 V_BB
III
II
90°
V_SIN+
0.748 V_BB
180°
V_COS−
Figure 3. Gauge Response
To drive the gauge’s pointer to a particular angle, the
microcontroller sends a 10−bit digital word into the serial
port. These 10 bits are divided as shown in Figure 4.
MSB
Gauge _{D9 D8 D7}
(360°)
D9−D7 select
which octant
LSB
D6 D5 D4 D3 D2 D1 D0
Divides a 45° octant into 128 equal parts to
achieve a 0.35° resolution Code 0−127₁₀
Figure 4. Definition of Serial Word
However, from a software programmers viewpoint, a
360° circle is divided into 1024 equal parts of 0.35° each.
Table 1 shows the data associated with the 45° divisions of
the 360° driver.
Table1. Nominal Output (V_BB = 14 V)
Input Code
Ideal
(Decimal) Degrees
Nominal
Degrees
V_SIN
(V)
V_COS
(V)
0
0
0.176
0.032 10.476
128
45
45.176
10.476 10.412
256
90
90.176
10.476 −0.032
384
135
135.176 10.412 −10.476
512
180
180.176 −0.032 −10.476
640
225
225.176 −10.476 −10.412
768
270
270.176 −10.476 0.032
896
315
315.176 −10.476 10.476
1023
359.65
359.826 −0.032 10.476
The 10 bits are shifted into the device’s shift register MSB
first using an SPI compatible scheme. This method is shown
in Figure 5. The CS must be high and remain high for SCLK
to be enabled. Data on SI is shifted in on the rising edge of
the synchronous clock signal. Data in the shift register
changes at SO on the falling edge of SCLK. This
arrangement allows the cascading of devices. SO is always
enabled. Data shifts through without affecting the outputs
until CS is brought low. At this time the internal DAC is
updated and the outputs change accordingly.
CS
SCLK
SI_(Setup)
SI
CS_Setup
SI_(Hold)
CS_Hold
SO
SO_{(Rise, Fall)}
10% − 90%
SI_(tpd)
Figure 5. Serial Data Timing Diagram
Figure 6 shows the power−up sequence for the CS4192.
Note the IC requires a pulse on the Chip Select (CS) pin to
clear the Status Fault (ST) after power up. OE must be high
before the falling edge of CS to enable the output buffers.
V_CC
CS
SI
10
Bits
10
Bits
OE
ST
OUTPUTS
ENABLED
OUTPUTS
ENABLED
Figure 6. Power Up Sequence
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