CS2082 Datasheet, PDF (6/12 Pages) ON Semiconductor – Dual Airbag Deployment ASIC

CS2082
PACKAGE PIN DESCRIPTION (continued)
Package Lead Number
SO–20L
18
19
20
Pin Symbol
D_IN
V_CC
GND
Serial Port Input.
5.0 V Regulated Supply.
Signal Ground.
Function
FUNCTIONAL DESCRIPTION
The CS2082 is an automotive air bag deployment and
diagnostic system for up to two independent firing loops.
Communication with the ASIC is through a synchronous
serial port using Serial Peripheral Interface (SPI) protocol,
at CLK rates up to 2.0 MHz.
Data is simultaneously sent from the D_OUT pin and
received at the D_IN pin under the control of the CS and CLK
pins. Error detection logic is included in the SPI to guard
against glitches on either the CS or CLK logic signal inputs.
A valid CS frame must contain exactly 8 CLK cycles for
each CS low–high–low transition. Detection of a frame error
will cause input data for that frame to be ignored and an error
code ($FE) to be sent during the next valid CS frame.
The data at D_OUT is sent MSB first and is guaranteed valid
before the rising edge of CLK. The 8 bits sent from D_OUT
after CS goes high will be the previous data received, data
from either the status register or the fault register, or the CS
frame error code ($FE).
The data at D_IN is received MSB first and must be valid
before the rising edge of CLK. The 8 bits received at D_IN
before CS goes low will be the current command. Table 1
defines the legal 8–bit SPI commands, where d = four data
bits and x = don’t care. All other inputs will be ignored.
Table 1. Valid CS2082 SPI Commands
COMMAND
FUNCTION
$1x
Read Staus Register
$2x
Read Fault Register
$3d
Squib Resistance Measurements
$4d
Analog MUX Select
$5d
Low Side Switch Control
$6d
Auxiliary Control Register
$Ad
High Side Switch Control
Read Status Register – $1x
The $1x command causes the data contained in the status
register to be sent from D_OUT during the next valid CS
frame. The status register reports the condition of the firing
paths, closure detection of an external safing switch between
the V_RES and VR1 pins, the state of the internal charge
pump, and the state of external V_BAT and V_RES power
supplies. The status register is an 8–bit active–high register
with bit definition as shown in Table 2.
Table 2. Status Register Bit Definition
BIT
VALUE
DESCRIPTION
D7
0
Always Logic zero
D6
0
Always Logic zero
D5
F1 SH1 and SL1 switches active
D4
F2 SH2 and SL2 switches active
D3
SSC Safing Sensor is closed
D2
RL
V_RES voltage is below trip
D1
BL
V_BAT voltage is below trip
D0
CL CHRG voltage is below trip
Read Fault Register – $2x
The $2x command causes the data contained in the fault
register to be sent from D_OUT during the next valid CS
frame. The register reports fire path faults by continuously
comparing each path to a portion of the voltage at the V_BAT
pin. The fault register is an 8–bit active–high register with
bit definition as shown in Table 3.
Table 3. Fault Register Bit Definition
BIT
VALUE
DESCRIPTION
D7
0
Always Logic zero
D6
0
Always Logic zero
D5
0
Always Logic zero
D4
0
Always Logic zero
D3
SB2 High Side of Sqib 2 above
75% V_BAT trip threshold
D2
SB1 High Side of Sqib 1 above
75% V_BAT trip threshold
D1
SG2 Low Side of Sqib 2 below
25% V_BAT trip threshold
D0
SG1 Low Side of Sqib 1 below
25% V_BAT trip threshold
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