CAV24C128 Datasheet, PDF (6/11 Pages) ON Semiconductor – CMOS Serial EEPROM

CAV24C128
Write Operations
Byte Write
Upon receiving a Slave address with the R/W bit set to ‘0’,
the CAV24C128 will interpret the next two bytes as address
bytes. These bytes are used to initialize the internal address
counter; the 2 most significant bits are ‘don’t care’, the next
8 point to one of 256 available pages and the last 6 point to
a location within a 64 byte page. A byte following the
address bytes will be interpreted as data. The data will be
loaded into the Page Write Buffer and will eventually be
written to memory at the address specified by the 14 active
address bits provided earlier. The CAV24C128 will
acknowledge the Slave address, address bytes and data byte.
The Master then starts the internal Write cycle by issuing a
STOP condition (Figure 6). During the internal Write cycle
(t_WR), the SDA output will be tri−stated and additional Read
or Write requests will be ignored (Figure 7).
Page Write
By continuing to load data into the Page Write Buffer after
the 1^st data byte and before issuing the STOP condition, up
to 64 bytes can be written simultaneously during one
internal Write cycle (Figure 8). If more data bytes are loaded
than locations available to the end of page, then loading will
continue from the beginning of page, i.e. the page address is
latched and the address count automatically increments to
and then wraps−around at the page boundary. Previously
loaded data can thus be overwritten by new data. What is
eventually written to memory reflects the latest Page Write
Buffer contents. Only data loaded within the most recent
Page Write sequence will be written to memory.
Acknowledge Polling
The ready/busy status of the CAV24C128 can be
ascertained by sending Read or Write requests immediately
following the STOP condition that initiated the internal
Write cycle. As long as internal Write is in progress, the
CAV24C128 will not acknowledge the Slave address.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAV24C128. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAV24C128 will not acknowledge the data
byte and the Write request will be rejected.
Delivery State
The CAV24C128 is shipped erased, i.e., all bytes are FFh.
BUS ACTIVITY: S
T
A _SLAVE
MASTER ^R ADDRESS
T
ADDRESS
BYTE
a₁₃−a₈
ADDRESS
BYTE
a₇−a₀
S
DATA
T
BYTE
O
P
S
**
P
SLAVE
A
A
A
A
C
C
C
C
K
K
K
K
* = Don’t Care Bit
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit
Byte n
ACK
t_WR
STOP
CONDITION
Figure 7. Write Cycle Timing
START
CONDITION
ADDRESS
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