CAV24C128 Datasheet, PDF (5/11 Pages) ON Semiconductor – CMOS Serial EEPROM

CAV24C128
SCL
SDA
START
CONDITION
Figure 2. START/STOP Conditions
STOP
CONDITION
DEVICE ADDRESS
1
0
1
0 A₂ A₁ A₀ R/W
Figure 3. Slave Address Bits
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
1
8
BUS RELEASE DELAY (RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ t_AA)
Figure 4. Acknowledge Timing
ACK SETUP (≥ t_SU:DAT)
t_F
t_HIGH
t_R
t_LOW
t_LOW
SCL
t_SU:STA
t_HD:STA
t_HD:DAT
t_SU:DAT
SDA IN
SDA OUT
t_AA
t_DH
Figure 5. Bus Timing
t_SU:STO
t_BUF
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