CAT9532_16 Datasheet, PDF (6/14 Pages) ON Semiconductor – 16-bit Programmable LED Dimmer

CAT9532
Pin Description
SCL: Serial Clock
The serial clock input clocks all data transferred into or out
of the device. The SCL line requires a pull−up resistor if it
is driven by an open drain output.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs. A pull−up resistor must be connected
from SDA line to V_CC.
LED0 to LED15: LED Driver Outputs / General Purpose
I/Os
The pins are open drain outputs used to drive directly
LEDs. Any of these pins can be programmed to drive the
LED ON, OFF, Blink Rate1 or Blink Rate2. When not used
for controlling the LEDs, these pins may be used as general
purpose parallel input/output.
RESET: External Reset Input
Active low Reset input is used to initialize the CAT9532
internal registers and the I²C state machine. The internal
registers are held in their default state while Reset input is
active. An external pull−up resistor of maximum 25 kW is
required when this pin is not actively driven.
Functional Description
The CAT9532 is a 16−bit I/O bus expander that provides
a programmable LED dimmer, controlled through an I²C
compatible serial interface.
The CAT9532 supports the I²C Bus data transmission
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
The CAT9532 operates as a Slave device. Both the Master
device and Slave device can operate as either transmitter or
receiver, but the Master device controls which mode is
activated.
I²C Bus Protocol
The features of the I²C bus protocol are defined as
follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition
(Figure 5).
START and STOP Conditions
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT9532 monitors the SDA and
SCL lines and will not respond until this condition is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT9532 for a read or
write operation. The four most significant bits of the slave
address are fixed as binary 1100 (Figure 6). The CAT9532
uses the next three bits as address bits.
The address bits A2, A1 and A0 are used to select which
device is accessed from maximum eight devices on the same
bus. These bits must compare to their hardwired input pins.
The 8th bit following the 7−bit slave address is the R/W bit
that specifies whether a read or write operation is to be
performed. When this bit is set to “1”, a read operation is
initiated, and when set to “0”, a write operation is selected.
Following the START condition and the slave address byte,
the CAT9532 monitors the bus and responds with an
acknowledge (on the SDA line) when its address matches the
transmitted slave address. The CAT9532 then performs a read
or a write operation depending on the state of the R/W bit.
SDA
SCL
START CONDITION
Figure 5. Start/Stop Timing
SLAVE ADDRESS
STOP CONDITION
1 1 0 0 A2 A1 A0 R/W
FIXED
PROGRAMMABLE
HARDWARE SELECTABLE
Figure 6. CAT9532 Slave Address
www.onsemi.com
6