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CAT5261_13 Datasheet, PDF (6/14 Pages) ON Semiconductor – Dual Digital Potentiometer (POT)
CAT5261
Table 6. PIN CAPACITANCE (Note 8) (TA = 25C, f = 1.0 MHz, VCC = 5 V, unless otherwise specified.)
Symbol
Test
Conditions
COUT (Note 8)
CIN (Note 8)
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD, A0, A1)
VOUT = 0 V
VIN = 0 V
Table 7. A.C. CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
tSU
Data Setup Time
50
tH
Data Hold Time
50
tWH
SCK High Time
125
tWL
SCK Low Time
125
fSCK
Clock Frequency
DC
tLZ
HOLD to Output Low Z
tRI (Note 8)
Input Rise Time
tFI (Note 8)
Input Fall Time
tHD
HOLD Setup Time
CL = 50 pF
100
tCD
HOLD Hold Time
100
tV
Output Valid from Clock Low
tHO
Output Hold Time
0
tDIS
Output Disable Time
tHZ
HOLD to Output High Z
tCS
CS High Time
2
tCSS
CS Setup Time
250
tCSH
CS Hold Time
250
8. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. POWER UP TIMING (Notes 9, 10)
Symbol
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
Parameter
Table 9. WIPER TIMING
Symbol
Parameter
Min
tWRPO
Wiper Response Time After Power Supply Stable
5
tWRL
Wiper Response Time After Instruction Issued
5
Table 10. WRITE CYCLE LIMITS
Symbol
tWR
Write Cycle Time
Parameter
Max
Units
8
pF
6
pF
Max
Units
ns
ns
ns
ns
3
MHz
50
ns
2
ms
2
ms
ns
ns
200
ns
ns
250
ns
100
ns
ns
ns
ns
Max
Units
1
ms
1
ms
Max
Units
10
ms
10
ms
Max
Units
5
ms
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