CAT5261_13 Datasheet, PDF (6/14 Pages) ON Semiconductor – Dual Digital Potentiometer (POT)

CAT5261
Table 6. PIN CAPACITANCE (Note 8) (T_A = 25C, f = 1.0 MHz, V_CC = 5 V, unless otherwise specified.)
Symbol
Test
Conditions
C_OUT (Note 8)
C_IN (Note 8)
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD, A0, A1)
V_OUT = 0 V
V_IN = 0 V
Table 7. A.C. CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
t_SU
Data Setup Time
50
t_H
Data Hold Time
50
t_WH
SCK High Time
125
t_WL
SCK Low Time
125
f_SCK
Clock Frequency
DC
t_LZ
HOLD to Output Low Z
t_RI (Note 8)
Input Rise Time
t_FI (Note 8)
Input Fall Time
t_HD
HOLD Setup Time
C_L = 50 pF
100
t_CD
HOLD Hold Time
100
t_V
Output Valid from Clock Low
t_HO
Output Hold Time
0
t_DIS
Output Disable Time
t_HZ
HOLD to Output High Z
t_CS
CS High Time
2
t_CSS
CS Setup Time
250
t_CSH
CS Hold Time
250
8. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. POWER UP TIMING (Notes 9, 10)
Symbol
t_PUR
t_PUW
Power-up to Read Operation
Power-up to Write Operation
Parameter
Table 9. WIPER TIMING
Symbol
Parameter
Min
t_WRPO
Wiper Response Time After Power Supply Stable
5
t_WRL
Wiper Response Time After Instruction Issued
5
Table 10. WRITE CYCLE LIMITS
Symbol
t_WR
Write Cycle Time
Parameter
Max
Units
8
pF
6
pF
Max
Units
ns
ns
ns
ns
3
MHz
50
ns
2
ms
2
ms
ns
ns
200
ns
ns
250
ns
100
ns
ns
ns
ns
Max
Units
1
ms
1
ms
Max
Units
10
ms
10
ms
Max
Units
5
ms
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