CAT28C16AL20 Datasheet, PDF (6/10 Pages) ON Semiconductor – 16 kb CMOS Parallel EEPROM

CAT28C16A
DATA Polling
DATA polling is provided to indicate the completion of a
byte write cycle. Once a byte write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O₇ (I/O₀–I/O₆ are
indeterminate) until the programming cycle is complete.
Upon completion of the self−timed byte write cycle, all I/O’s
will output true data during a read cycle.
t_WC
ADDRESS
t_AS
CE
t_AH
t_CW
t_DL
t_OEH
OE
t_OES
t_CS
t_CH
WE
DATA OUT
HIGH−Z
DATA IN
DATA VALID
t_DS
t_DH
Figure 6. Byte Write Cycle [CE Controlled]
ADDRESS
CE
WE
OE
I/O7
D_IN = X
t_OEH
t_OE
t_WC
D_OUT = X
Figure 7. DATA Polling
t_OES
D_OUT = X
Hardware Data Protection
The following is a list of hardware data protection features
that are incorporated into the CAT28C16A.
1. V_CC sense provides for write protection when V_CC
falls below 3.0 V min.
2. A power on delay mechanism, t_INIT (see AC
characteristics), provides a 5 to 20 ms delay before
a write sequence, after V_CC has reached 3.0 V
min.
3. Write inhibit is activated by holding any one of
OE low, CE high or WE high.
4. Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
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