CAT24WC66 Datasheet, PDF (6/11 Pages) Catalyst Semiconductor – 64K-Bit I2C Serial CMOS EEPROM

CAT24WC66
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8−bit
address words that are to be written into the address pointers
of the CAT24WC66. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the addressed memory location. The
CAT24WC66 acknowledges once more and the Master
generates the STOP condition. At this time, the device
begins an internal programming cycle to nonvolatile
memory. While the cycle is in progress, the device will not
respond to any request from the Master device.
Page Write
The CAT24WC66 writes up to 32 bytes of data, in a single
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to 31
additional bytes. After each byte has been transmitted,
CAT24WC66 will respond with an acknowledge, and
internally increment the five low order address bits by one.
The high order bits remain unchanged.
If the Master transmits more than 32 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 32 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT24WC66 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation,
CAT24WC66 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If CAT24WC66 is still busy with the write
operation, no ACK will be returned. If CAT24WC66 has
completed the write operation, an ACK will be returned and
the host can then proceed with the next read or write
operation.
Write Protection
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array. If the
WP pin is tied to VCC, the top 1/4 of the memory array
(locations 1800H to 1FFF) is protected and becomes read
only. The CAT24WC66 will accept both slave and byte
addresses, but the memory location accessed is protected
from programming by the device’s failure to send an
acknowledge after the first byte of data is received.
S
T
BUS ACTIVITY:
MASTER
A
R
T
SLAVE
ADDRESS
BYTE ADDRESS
A₁₅−A₈
A₇−A₀
S
T
DATA
O
P
SDA LINE S
XX X
P
A
A
A
A
C
C
C
C
K
K
K
K
Figure 7. Byte Write Timing
S
BUS T
ACTIVITY: ^A
MASTER
R
T
SLAVE
ADDRESS
BYTE ADDRESS
A₁₅−A₈
A₇−A₀
DATA
SDA LINE S
XX X
A
A
A
A
C
C
C
C
K
K
K
K
Figure 8. Page Write Timing
DATA n
A
C
K
S
T
DATA n+31
O
P
P
A
A
C
C
K
K
READ OPERATIONS
The READ operation for the CAT24WC66 is initiated in
the same manner as the write operation with one exception,
that R/W bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ, Selective/
Random READ and Sequential READ.
Immediate/Current Address Read
The CAT24WC66’s address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to address N,
the READ immediately following would access data from
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