CAT24WC66 Datasheet, PDF (5/11 Pages) Catalyst Semiconductor – 64K-Bit I2C Serial CMOS EEPROM

CAT24WC66
I²C Bus Protocol
The features of the I²C bus protocol are defined as
follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT24WC66 monitors the SDA
and SCL lines and will not respond until this condition is
met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8−bit slave address are fixed as 1010
(Figure 6). The next three bits (A2, A1, A0) are the device
address bits; up to eight 64K devices may to be connected to
the same bus. These bits must compare to the hardwired
input pins, A2, A1 and A0. The last bit of the slave address
specifies whether a Read or Write operation is to be
performed. When this bit is set to 1, a Read operation is
selected, and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC66 monitors the bus and
responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT24WC66 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT24WC66 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
When the CAT24WC66 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the line
for an acknowledge. Once it receives this acknowledge, the
CAT24WC66 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition. The
master must then issue a stop condition to return the
CAT24WC66 to the standby power mode and place the
device in a known state.
SCL FROM
1
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 5. Acknowledge Timing
ACKNOWLEDGE
1 0 1 0 A2 A1 A0 R/W
DEVICE ADDRESS
Figure 6. Slave Address Bits
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