CAT24C44LI-G Datasheet, PDF (6/9 Pages) ON Semiconductor – 256-Bit Serial Nonvolatile CMOS Static RAM

CAT24C44
WREN/WRDS
The CAT24C44 powers up in the program disable state
(the “write enable latch” is reset). Any programming after
power-up or after a WRDS (RAM write/EEPROM store
disable) instruction must first be preceded by the WREN
(RAM write/EEPROM store enable) instruction. Once
writing/storing is enabled, it will remain enabled until
power to the device is removed, the WRDS instruction is
sent, or an EEPROM store has been executed (STO).
The WRDS (write/store disable) can be used to disable
all CAT24C44 programming functions, and will prevent
any accidental writing to the RAM, or storing to the
EEPROM.
Data can be read normally from the CAT24C44 regard-
less of the “write enable latch” status.
Figure 3. Read Cycle Timing
SK CYCLE # 6
7
8
9
10
SK
VIH
CE
tPD
DI
tPD
HIGH-Z
DO
D0
D1
11
tZ
HIGH-Z
Dn
Figure 4. Write Cycle Timing
tSKH
1/FSK
tSKL
SK
x
1
2
tCES
CE
tDS
tDH
DI
n
tCEH
tCDS
Doc. No. MD-1083, Rev. T
6
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice