BUL642D2 Datasheet, PDF (6/8 Pages) ON Semiconductor – High Speed, High Gain Bipolar NPN Transistor with Integrated Collector−Emitter and Built−in Efficient Antisaturation Network

BUL642D2
3.0
V_CC = 125 V, Pw = 100 mS, G = 10
I_b2 = I_C/2 @ 125°C
2.0
I_b2 = I_C @ 125°C
1.0
I_b2 = I_C/2 @ 25°C
0
0.1
I_b2 = I_C @ 25°C
0.3 0.5 0.7 0.9 1.1 1.3
I_C, COLLECTOR CURRENT (AMP)
Figure 13. Resistive Switch Time,
Storage Time
750
650 ^{Ib2 = IC/2 @ 125°C}
V_CC = 125 V, Pw = 100 mS, G = 10
550
450 _{Ib2 = IC @ 25°C}
350
250 ^{Ib2 = IC/2 @ 25°C}
150
I_b2 = I_C @ 125°C
50
1.5
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5
I_C, COLLECTOR CURRENT (AMP)
Figure 14. Resistive Switch Time, Fall Time
100
5 ms
10
1.0
1 ms ^{10 ms}
1 ms
0.8
SECOND BREAKDOWN
DERATING
DC
1.0
0.1
0.01
10
100
V_CE, COLLECTOR−EMITTER VOLTAGE (V)
Figure 15.
0.6
0.4
0.2
1000
0
20
THERMAL DERATING
40
60 80 100 120
T_C, CASE TEMPERATURE (°C)
Figure 16. Power Derating
140 160
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I_C−V_CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate. The data of Figure 15 is
based on T_C = 25°C; T_j(pk) is variable depending on power
level. Second breakdown pulse limits do not derate like
thermal limitations. Allowable current at the voltages shown
on Figure 10 may be found at any case temperature by using
the appropriate curve on Figure 16.
T_j(pk) may be calculated from the data in Figure 18. At any
case temperatures, thermal limitations will reduce the power
that can be handled to values less than the limitations
imposed by second breakdown.
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