AMIS-42770 Datasheet, PDF (6/13 Pages) ON Semiconductor – Dual High Speed CAN Transceiver

AMIS−42770
Transmitters
The transceiver includes two transmitters, one for each bus
line, and a driver control circuit. Each transmitter is
implemented as a push and a pull driver. The drivers will be
active if the transmission of a dominant bit is required. During
the transmission of a recessive bit all drivers are passive. The
transmitters have a built−in current limiting circuit that
protects the driver stages from damage caused by accidental
short circuit to either positive supply voltage or to ground.
Additionally a thermal protection circuit is integrated.
The driver control circuit ensures that the drivers are
switched on and off with a controlled slope to limit EME.
The driver control circuit will control itself by the thermal
protection circuit, the timer circuit and the logic unit.
The enable signal ENBx allows the transmitter to be
switched off by a third device (e.g. the °C). In the disabled
state (ENBx = high) the corresponding transmitter behaves
as in the recessive state.
Table 3. FUNCTION OF THE LOGIC UNIT (bold letters describe input signals)
EN1B
EN2B
TX0
TEXT
Bus 1 State
Bus 2 State
RX0
RINT
0
0
0
0
dominant
dominant
0
0
0
0
0
1
dominant
dominant
0
0
0
0
1
0
dominant
dominant
0
1
0
0
1
1
recessive
recessive
1
1
0
0
1
1
dominant (Note 3)
dominant
0
0
0
0
1
1
dominant
dominant (Note 3)
0
0
0
1
0
0
dominant
recessive
0
0
0
1
0
1
dominant
recessive
0
0
0
1
1
0
dominant
recessive
0
1
0
1
1
1
recessive
recessive
1
1
0
1
1
1
dominant (Note 3)
recessive
0
0
0
1
1
1
recessive
dominant (Note 3)
1
1
1
0
0
0
recessive
dominant
0
0
1
0
0
1
recessive
dominant
0
0
1
0
1
0
recessive
dominant
0
1
1
0
1
1
recessive
recessive
1
1
1
0
1
1
dominant (Note 3)
recessive
1
1
1
0
1
1
recessive
dominant (Note 3)
0
0
1
1
0
0
recessive
recessive
0
0
1
1
0
1
recessive
recessive
0
0
1
1
1
0
recessive
recessive
0
1
1
1
1
1
recessive
recessive
1
1
1
1
1
1
dominant (Note 3)
recessive
1
1
1
1
1
1
recessive
dominant (Note 3)
1
1
3. Dominant detected by the corresponding receiver.
Receivers
Two bus receiving sections sense the states of the bus
lines. Each receiver section consists of an input filter and a
fast and accurate comparator. The aim of the input filter is
to improve the immunity against high−frequency
disturbances and also to convert the voltage at the bus lines
CANHx and CANLx, which can vary from –12 V to +12 V,
to voltages in the range 0 to 5 V, which can be applied to the
comparators.
The output signal of the comparators is gated by the ENBx
signal. In the disabled state (ENBX = high), the output signal
of the comparator will be replaced by a permanently
recessive state and does not depend on the bus voltage. In the
enabled state the receiver signal sent to the logic unit is
identical to the comparator output signal.
Time−out Counter
To avoid that the transceiver drives a permanent dominant
state on either of the bus lines (blocking all communication),
time−out function is implemented. Signals on pins Tx0 and
Text as well as both bus receivers are connected to the logic
unit through independent timers. If the input of the timer
stays dominant for longer than 25 ms (see parameter t_dom),
it is replaced by a recessive signal on the timer output.
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