AMIS-42770 Datasheet, PDF (5/13 Pages) ON Semiconductor – Dual High Speed CAN Transceiver

AMIS−42770
Table 2. PIN DESCRIPTION
Pin
Name
Description
1
NC
Not connected
2
ENB2
Enable input, bus system 2; internal pull−up
3
Text
Multi−system transmitter Input; internal pull−up
4
Tx0
Transmitter input; internal pull−up
5
GND
Ground connection (Note 2)
6
GND
Ground connection (Note 2)
7
Rx0
Receiver output
8
V_REF1
Reference voltage
9
Rint
Multi−system receiver output
10
ENB1
Enable input, bus system 1; internal pull−up
11
NC
Not connected
12
VCC
Positive supply voltage
13
CANH1
CANH transceiver I/O bus system 1
14
CANL1
CANL transceiver I/O bus system 1
15
GND
Ground connection (Note 2)
16
GND
Ground connection (Note 2)
17
GND
Ground connection (Note 2)
18
CANL2
CANL transceiver I/O bus system 2
19
CANH2
CANH transceiver I/O bus system 2
20
NC
Not connected
2. In order to ensure the chip performance, all these pins need to be connected to GND on the PCB.
FUNCTIONAL DESCRIPTION
Overall Functional Description
AMIS−42770 is specially designed to provide the link
between the protocol IC (CAN controller) and two physical
bus lines. Data interchange between those two bus lines is
realized via the logic unit inside the chip. To provide an
independent switch−off of the transceiver units for both bus
systems by a third device (e.g. the °C), enable−inputs for the
corresponding driving and receiving sections are provided.
As long as both lines are enabled, they appear as one logical
bus to all nodes connected to either of them.
The bus lines can have two logical states, dominant or
recessive. A bus is in the recessive state when the driving
sections of all transceivers connected to the bus are passive.
The differential voltage between the two wires is
approximately zero. If at least one driver is active, the bus
changes into the dominant state. This state is represented by
a differential voltage greater than a minimum threshold and
therefore by a current flow through the terminating resistors
of the bus line. The recessive state is overwritten by the
dominant state.
In case a fault (like short circuit) is present on one of the
bus lines, it remains limited to that bus line where it occurs.
Data interchange from the protocol IC to the other bus
system and on this bus system itself can be continued.
AMIS−42770 can be also used for only one bus system. If
the connections for the second bus system are simply left
open it serves as a single transceiver for an electronic unit.
For correct operation, it is necessary to terminate the open
bus by the proper termination resistor.
Logic Unit and CAN Controller Interface
The logic unit inside AMIS−42770 provides data transfer
from/to the digital interface to/from the two busses and from
one bus to the other bus. The detailed function of the logic
unit is described in Table 3.
All digital input pins, including ENBx, have an internal
pull−up resistor to ensure a recessive state when the input is
not connected or is accidentally interrupted. A dominant state
on the bus line is represented by a low−level at the digital
interface; a recessive state is represented by a high−level.
Dominant state received on any bus (if enabled) causes a
dominant state on both busses, pin Rint and pin Rx0.
Dominant signal on any of the input pins Tx0 and Text causes
transmission of dominant on both bus lines (if enabled).
Digital inputs Tx0 and Text are used for connecting the
internal logic’s of several IC’s to obtain versions with more
than two bus outputs (see Figure 4). They have also a direct
logical link to pins Rx0 and Rint independently on the EN1x
pins – dominant on Tx0 is directly transferred to both Rx0
and Rint pins, dominant on Text is only transferred to Rx0.
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