AMIS-4168X Datasheet, PDF (6/20 Pages) AMI SEMICONDUCTOR – Fault Tolerant CAN Transceiver

AMIS-4168x
7.0 Functional Description
7.1 Description
AMIS-41682 is a fault tolerant CAN transceiver which works as an interface between the CAN protocol controller and the physical wires
of the CAN bus (see Figure 2: Application Diagram AMIS-41682). It is primarily intended for low speed applications, up to 125kBaud, in
passenger cars. The device provides differential transmit capability to the CAN bus and differential receive capability to the CAN
controller.
The AMIS-41683 has open-drain outputs (RXD and ERR-B pins), which allow the user to use external pull-up resistors to the required
supply voltage; this can be 5V or 3.3V.
To reduce EME, the rise and fall slope are limited. Together with matched CANL and CANH output stages, this allows the use of an
unshielded twisted pair or a parallel pair of wires for the bus lines.
The failure detection logic automatically selects a suitable transmission mode, differential or single-wire transmission. Together with the
transmission mode, the failure detector will configure the output stages in such a way that excessive currents are avoided and the
circuit returns to normal operation when the error is removed.
A high common-mode range for the differential receiver guarantees reception under worst case conditions and together with the
integrated filter the circuit realizes an excellent immunity against EMS. The receivers connected to pins CANH and CANL have
threshold voltages that ensure a maximum noise margin in single-wire mode.
A timer has been integrated at pin TXD. This timer prevents the AMIS-41682 from driving the bus lines to a permanent dominant state.
7.2 Failure Detector
The failure detector is fully active in the normal operating mode. After the detection of a single bus failure the detector switches to the
appropriate mode. The different wiring failures are depicted in Figure 5: Different Types of Wiring Failure. The figure also indicates the
effect of the different wiring failures on the transmitter and the receiver. The detection circuit itself is not depicted.
The differential receiver threshold voltage is typically set at 3V (VCC = 5V). This ensures correct reception with a noise margin as high
as possible in the normal operating mode and in the event of failures 1, 2, 4, and 6a. These failures, or recovery from them, do not
destroy ongoing transmissions. During the failure, reception is still done by the differential receiver and the transmitter stays fully active.
To avoid false triggering by external RF influences the single-wire modes are activated after a certain delay time. When the bus failure
disappears for another time delay, the transceiver switches back to the differential mode. When one of the bus failures 3, 5, 6, 6a, and
7 is detected, the defective bus wire is disabled by switching off the affected bus termination and the respective output stage. A wake-
up from sleep mode via the bus is possible either by way of a dominant CANH or CANL line. This ensures that a wake-up is possible
even if one of the failures 1 to 7 occurs. If any of the wiring failure occurs, the output signal on pin ERRB will become low. On error
recovery, the output signal on pin ERRB will become high again.
During all single-wire transmissions, the EMC performance (both immunity and emission) is worse than in the differential mode. The
integrated receiver filters suppress any HF noise induced into the bus wires. The cut-off frequency of these filters is a compromise
between propagation delay and HF suppression. In the single-wire mode, LF noise cannot be distinguished from the required signal.
Rev. 4 | Page 6 of 20 | www.onsemi.com