AMIS-30660 Datasheet, PDF (6/10 Pages) AMI SEMICONDUCTOR – High Speed CAN Transceiver

AMIS−30660
Table 6. DC AND TIMING CHARACTERISTICS V_CC = 4.75 V to 5.25 V; T_junc = −40°C to +150°C; R_LT = 60 W unless specified
otherwise.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BUS LINES (Pins CANH and CANL)
I_{o(sc) (CANL)}
Short circuit output current at pin
V _CANL = 36V; V_TxD =
45
70
CANL
0V
120
mA
V_i(dif)(th)
Differential receiver threshold
−5 V < V_CANL < +10 V;
0.5
0.7
0.9
V
voltage
−5 V < V_CANH < +10 V;
See Figure 4
V_{ihcm(dif) (th)}
Differential receiver threshold
−35 V < V_CANL < +35 V;
0.25
0.7
1.05
V
voltage for high common−mode
−35 V < V_CANH < +35V;
See Figure 4
V_{i(dif) (hys)}
Differential receiver input voltage
−5 V < V_CANL < +10 V;
50
70
hysteresis
−5 V < V_CANH < +10 V;
See Figure 4
100
mV
R_i(cm)(CANH)
Common−mode input resistance at
pin CANH
15
25
37
KW
R_{i(cm) (CANL)}
Common−mode input resistance at
pin CANL
15
25
37
KW
R_i(cm)(m)
Matching between pin CANH and
pin CANL common−mode input res-
istance
V_CANH = V_CANL
−3
0
+3
%
R_i(dif)
C_i(CANH)
C_i(CANL)
C_i(dif)
I_LI(CANH)
I_LI(CANL)
V_CM−peak
Differential input resistance
25
50
75
KW
Input capacitance at pin CANH
V_TxD = V_CC; not tested
7.5
20
pF
Input capacitance at pin CANL
V_TxD = V_CC; not tested
7.5
20
pF
Differential input capacitance
V_TxD = V_CC; not tested
3.75
10
pF
Input leakage current at pin CANH
V_CC = 0 V; V_CANH = 5V
10
170
250
mA
Input leakage current at pin CANL
V_CC = 0 V; V_CANL = 5V
10
170
250
mA
Common−mode peak during trans-
ition from dom → rec or rec → dom
See Figures 7 and 8
−500
500
mV
V_CM−step
Difference in common−mode
between dominant and recessive
state
See Figures 7 and 8
−150
150
mV
POWER−ON−RESET (POR)
PORL
POR level
CANH, CANL, V_ref in
2.2
3.5
4.7
V
tri−state below POR
level
THERMAL SHUTDOWN
T_j(sd)
Shutdown junction temperature
TIMING CHARACTERISTICS (see Figures 5 and 6)
150
160
180
°C
t_{d(TxD−BUSon)}
t_{d(TxD−BUSoff)}
t_{d(BUSon−RxD)}
t_{d(BUSoff−RxD)}
t_{pd(rec−dom)}
Delay TxD to bus active
Delay TxD to bus inactive
Delay bus active to RxD
Delay bus inactive to RxD
Propagation delay TxD to RxD from
recessive to dominant
V_s = 0 V
V_s = 0 V
V_s = 0 V
V_s = 0 V
V_s = 0 V
40
85
130
ns
30
60
105
ns
25
55
105
ns
65
100
135
ns
70
245
ns
t_{d(dom−rec)}
Propagation delay TxD to RxD from V_s = 0 V
100
dominant to recessive
245
ns
t_dom(TxD)
TxD dominant time for time out
V_TxD = 0 V
250
450
750
ms
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