TCP-3012H Datasheet, PDF (5/9 Pages) ON Semiconductor – 1.2 pF Passive Tunable Integrated Circuits (PTIC)

TCP−3012H
Wafer Level Chip Scale Package (WLCSP) Layout and Dimensional Information
D3
A2
D2
(Copper Pillar
Height)
D1
C1
C2
C3
N/C Bias
B3
A1
RF1 RF2
RF1 RF2
B2
RF1 RF2
2X 0.104 mm (Typ)
(Copper Pillar)
2X 0.069 mm (Typ)
(Copper Pillar)
RF Pillars
0.104 mm (Typ)
Top View
(Pillars Down)
Note:
2X means 2 sites with the specific value
3X means 3 sites with the specific value
4X means 4 sites with the specific value
Side View
B4
B1
Bottom View
(Pillars Up)
Figure 7. WLCSP Package Dimensions
RF Pillars
0.069 mm (Typ)
Table 3. PACKAGE DIMENSIONS
(All dimensions are in millimeters)
WLCSP* DIM Nominal Max
8P
A1
0.879
10P
A1
1.029
12P
A1
1.179
14P
A1
1.329
ALL
A2
0.722
ALL
B1
0.460
ALL
B2
0.150
ALL
B3
0.300
ALL
B4
0.131
ALL
C1
0.1485
ALL
C2
0.425
ALL
C3
0.130
ALL
D1
0.530
ALL
D2
0.081
ALL
D3
0.611
*Total number of pillars
Device
1.2, 2.7 pF
3.3, 3.9 pF
4.7, 5.6, 6.8, 8.2 pF
Note:
0.9 mm pad layout is standard for all products. Shorter pad
layouts can be considered for smaller products.
Figure 8. Recommended Pad Layout
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