NSS12200WT1G Datasheet, PDF (5/6 Pages) ON Semiconductor – 12 V, 3 A, Low VCE(sat) PNP Transistor

NSS12200WT1G
PACKAGE DIMENSIONS
D
e
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.
6
5
4
H_E
−E−
1
2
3
b 6 PL
0.2 (0.008) M E M
A3
C
A
MILLIMETERS
INCHES
DIM MIN NOM MAX MIN NOM MAX
A 0.80 0.95 1.10 0.031 0.037 0.043
A1 0.00 0.05 0.10 0.000 0.002 0.004
A3
0.20 REF
0.008 REF
b 0.10 0.21 0.30 0.004 0.008 0.012
C 0.10 0.14 0.25 0.004 0.005 0.010
D 1.80 2.00 2.20 0.070 0.078 0.086
E 1.15 1.25 1.35 0.045 0.049 0.053
e
0.65 BSC
0.026 BSC
L 0.10 0.20 0.30 0.004 0.008 0.012
H_E 2.00 2.10 2.20 0.078 0.082 0.086
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
A1
L
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.40
0.0157
0.65
0.025
1.9
0.0748
ǒ Ǔ _{SCALE 20:1}
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
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