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NLV17SZ74USG Datasheet, PDF (5/6 Pages) ON Semiconductor – Single D Flip Flop
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NL17SZ74
Vcc
D
50%
0V
ts
th
tw
Vcc
CP
50%
fmax
tPLH, tPHL
0V
VOH
Q,
50%
Q
VOL
WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES
tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Vcc
PR
50%
0V
CLR
tPLH
Vcc
50%
0V
tPHL
Q
50%
50%
VOL
tPLH
VOH
Q
50%
tPHL
50%
WAVEFORM 2 − PROPAGATION DELAYS
tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
tw
Vcc
PR, CLR
50%
0V
trec
Vcc
CP
50%
tw
0V
WAVEFORM 3 − RECOVERY TIME
tR = tF = 3.0 ns from 10% to 90%; f = 1 MHz; tw = 500 ns
Output Reg: VOL ≤ 0.8 V, VOH ≥ 2.0 V
Figure 1. AC Waveforms
PULSE
GENERATOR
VCC
DUT
RT
CL
RL
Figure 2. Test Circuit
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