NB7L216 Datasheet, PDF (5/12 Pages) ON Semiconductor – 2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination

NB7L216
Table 5. AC CHARACTERISTICS V_CC = 2.375 V to 3.465 V, V_EE = 0 V; (Note 12)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
V_OUTPP Output Voltage Amplitude (@ V_INPPmin)f_in ≤ 7.0 GHz 275 380
275 380
275 380
mV
(See Figure 4)
f_in ≤ 8.5 GHz 100 250
100 250
100 250
f_DATA Maximum Operating Data Rate
10 12
10 12
10 12
Gb/s
|S21| Power Gain DC to 7 GHz
35
35
35
dB
|S11| Input Return Loss @ 7 GHz
−10
−10
−10
dB
|S22| Output Return Loss @ 7 GHz
−5
−5
−5
dB
|S12| Reverse Isolation (Differential Configuration)
−25
−25
−25
dB
IIP3
Input Third Order Intercept
0
0
0
dBm
t_PLH,
t_PHL
t_SKEW
Propagation Delay to Output Differential @ 1 GHz
Duty Cycle Skew (Note 12)
Device to Device Skew (Note 17)
60 120 180 60 120 180 60 120 180 ps
2 10
5 20
2 10
5 20
2
10 ps
5
20
t_JITTER
RMS Random Clock Jitter
(Note 15)
f_in v 8.5 GHz
Peak−to−Peak Data Dependent Jitter (Note 16)
f_DATA = 3.5 Gb/s
f_DATA = 5.0 Gb/s
f_DATA = 10 Gb/s
f_DATA = 12 Gb/s
0.1 0.5
1
7
3
9
4
9
4
9
V_INPP Input Voltage Swing/Sensitivity
20
(Differential Configuration) (Note 14 and Figure 12)
2500 20
0.1 0.5
1
7
3
9
4
9
4
9
2500 20
0.1 0.5 ps
1
7
3
9
4
9
4
9
2500 mV
t_r
Output Rise/Fall Times @ 0.5 GHz Q, Q
t_f
(20% − 80%)
30 45
30 45
30 45 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values
are applied individually under normal operating conditions and not valid simultaneously.
12. Measured by forcing V_INPPmin from a 50% duty cycle clock source. All loading with an external R_L = 50 W to V_TT =V_CC − 2.0 V. Input edge
rates 40 ps (20% − 80%).
13. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz.
14. V_INPP (MAX) cannot exceed V_CC − V_EE. Input voltage swing is a single−ended measurement operating in differential mode.
15. Additive RMS jitter with 50% duty cycle clock signal.
16. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 2²³âˆ’1.
17. Device to device skew is measured between outputs under identical transition @ 1 GHz.
500
450
400
−40°C
350
85°C
300
250
25°C
200
150
100
50
0
0 2 4 6 7 8 9 10 11 12
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (V_OUTPP) versus
Input Clock Frequency (f_IN) and Temperature
(V_INPP = 400 mV, V_CC = 3.3 V and V_EE = 0 V)
500
450
400
−40°C
350
300
250
85°C
200
25°C
150
100
50
0
0 2 4 6 7 8 9 10 11 12
INPUT CLOCK FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (V_OUTPP) versus
Input Clock Frequency (f_IN) and Temperature
(V_INPP = 20 mV, V_CC = 3.3 V and V_EE = 0 V)
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