NB7L216 Datasheet, PDF (1/12 Pages) ON Semiconductor – 2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination

NB7L216
2.5V/3.3V, 12Gb/s Multi
Level Clock/Data Input to
RSECL, High Gain
Receiver/Buffer/Translator
with Internal Termination
Description
The NB7L216 is a differential receiver/driver with high gain output
targeted for high frequency applications. The device is functionally
equivalent to the NBSG16 but with much higher gain output. This
highly versatile device provides 35 dB of gain up to 7 GHz.
Inputs incorporate internal 50 W termination resistors and accept
Negative ECL (NECL), Positive ECL (PECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are Reduced Swing ECL (RSECL), 400 mV.
The V_BB pin is an internally generated voltage supply available to
this device only. V_BB is used as a reference voltage for single−ended
NECL or PECL inputs. For all single−ended input conditions, the
unused complementary differential input should be connected to V_BB
as a switching reference voltage. V_BB may also rebias AC coupled
inputs. When used, decouple V_BB via a 0.01 mF capacitor and limit
current sourcing or sinking to 0.5 mA. When not used, V_BB output
should be left open.
Application notes, models and support documentation are available
at www.onsemi.com.
Features
• High Gain of 35 dB from DC to 7 GHz Typical
• High IIP3: 0 dBm Typical
• 20 mV Minimum Input Voltage Swing
• Maximum Input Clock Frequency up to 8.5 GHz
• Maximum Input Data Rate up to 12 Gb/s Typical
• <0.5 ps of RMS Clock Jitter
• <9 ps of Data Dependent Jitter
• 120 ps Typical Propagation Delay
• 30 ps Typical Rise and Fall Times
• RSPECL Output with Operating Range: V_CC = 2.375 V to 3.465 V
with V_EE = 0 V
• RSNECL Output with RSNECL or NECL Inputs with Operating
Range: V_CC = 0 V with V_EE = −2.375 V to −3.465 V
• RSECL Output Level (400 mV Peak−to−Peak Output),
• 50 W Internal Input Termination Resistors (Temperature−Coefficient
of < 6.38 mW/°C)
• VBB – ECL Reference Voltage Output
• Pb−Free Packages are Available
http://onsemi.com
MARKING DIAGRAM*
QFN−16
MN SUFFIX
CASE 485G
16
1
NB7L
216
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
50 W
D
Q
D
Q
50 W
VTD
Figure 1. Functional Block Diagram
Device DDJ = 3 ps
TIME (17 ps/div)
Figure 2. Typical Output Waveform at
12 Gb/s with PRBS 2²³âˆ’1 (V_INPP = 400 mV,
Input Signal DDJ = 12 ps)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
August, 2006 − Rev. 2
Publication Order Number:
NB7L216/D