NB3H5150-01 Datasheet, PDF (5/19 Pages) ON Semiconductor – Low Noise Multi-Rate Clock Generator

NB3H5150−01
When REFMODE is HIGH, the CLK_XTAL1 and
CLK_XTAL2 differential input pins have internal AC
coupling capacitors selected with self−bias circuity for the
differential input buffer. This differential buffer will directly
accept any differential signal including LVPECL, LVDS,
HCSL or CML. Drive the CLK_XTAL1 pin with the true
signal and the CLK_XTAL2 pin with the complementary
signal.
When overdriving the CLK_XTAL1 input pin with a
single−ended signa set REFMODE to a HIGH, and connect
CLK_XTAL2 to Ground. The input has internal AC
coupling capacitor with self−bias circuitry.
Table 2. CRYSTAL INPUT INTERFACE AND REFMODE TRUTH TABLE
Input Mode Crystal/External Clock
REFMODE
CLK_XTAL1
Crystal
LOW
Use a Crystal
Any Differential Input
HIGH
Overdrive with True Input
Single−Ended Input
HIGH
Overdrive
CLKb_XTAL2
Use a Crystal
Overdrive with Complementary Input
Connect to Ground
LVCMOS Outputs
LVCMOS outputs are powered with VDDOn = 3.3 V,
2.5 V or 1.8 V
A 33 W series terminating resistor may be used on each
clock output if the metal trace is longer than one inch.
Any unused LVCMOS output can be left floating, but
there should be no metal trace attached to the package pin.
LVPECL Differential Outputs
The differential LVPECL outputs are powered with
VDDO = 3.3 V or 2.5 V and must be properly loaded. See
Figure 10.
Any unused differential output pair should either be left
floating or terminated.
REF Out
In the PLL bypass mode available via I²C, the input
reference frequency can be routed to CLK1A and CLK1B as
phase aligned LVCMOS or differential LVPECL outputs
with the same frequency. The output frequency and duty
cycle equals the input frequency and duty cycle.
Power Supplies
The NB3H5150−01 has several power supply pins:
• VDD is the supply voltage for the input and digital core
circuitry.
• AVDD1, AVDD2 and AVDD3 powers the core analog
circuits. VDD = AVDD1 = AVDD2 = AVDD3.
• VDDO1, VDDO2, VDDO3 and VDDO4 are individual
power supplies for each of the four CLKnA/B output
banks.
Upon power−up, all four VDDOn pins must be connected
to a power supply, even if only one output is being used.
Any combination of VDD and VDDOn power supply
voltages is allowed.
A power supply filtering scheme in Figure 8 is
recommended for best device performance.
When all VDD, AVDDn and VDDOn pins reach their
minimum voltage per Table 10, the NB3H5150−01 will
operate at the proper output frequencies.
EP Exposed Pad
The exposed pad on the bottom side of the package must
be connected to Ground.
LDO Pins
The NB3H5150−01 has integrated low noise 1.8 V
Low−Drop−Out (LDO) voltage regulators which provide
power internal to the NB3H5150−01.
The LDOs require decoupling capacitors in the range of
1 mF to 10 mF for compensation and high frequency PSR.
When powered−down, the device turns off the LDOs and
enters a low power shutdown mode consuming less than
1 mA.
FTM
This is a Factory Test Mode pin and must be connected to
the Ground of the application for proper operation.
PIN−STRAP / FSn Frequency Select MODE: (see
Tables 3 and 4)
The NB3H5150−01 can be configured to operate in
pin−strap mode where the control pins FSnA/B can be set to
generate the necessary clock outputs of the device.
Prerequisites:
♦ SDA and SCL/PD must be Low at all times while in
pin−strap mode to enable FS control. If SDA ever
goes High, pin−strap is exited and the only way to
go back is to power cycle the device.
♦ Mixed Mode Control pin (MMC) level will be
IGNORED.
Sequencing:
1. Upon device power−up (assuming SCL is LOW)
a. All four CLK(n) frequency and output type
selections will be pre−loaded according to the
FS pin settings, but all four outputs will be held
at static LVPECL levels (CLKnA = Low,
CLKnB = High) until the PLL has become
stable.
b. After the PLL is stable, all CLK(n) output type
selections (i.e. LVPECL or LVCMOS) will
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