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NB3H5150-01 Datasheet, PDF (1/19 Pages) ON Semiconductor – Low Noise Multi-Rate Clock Generator | |||
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NB3H5150-01
2.5V / 3.3V Low Noise
Multi-Rate Clock Generator
Description
The NB3H5150â01 is a high performance MultiâRate Clock
generator which simultaneously synthesizes up to four different
frequencies from a single PLL using a 25 MHz input reference. The
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reference frequency can be provided by a crystal, LVCMOS/LVTTL,
LVPECL, HCSL or LVDS differential signals. The REFMODE pin
will select the reference source.
MARKING
DIAGRAM*
Three output banks (CLK1A/CLK1B to CLK3A/CLK3B) produce
user selectable frequencies of: 33.33 MHz, 50 MHz, 100 MHz,
125 MHz, or 156.25 MHz and have ultraâlow noise/jitter performance
of less than 0.3 ps.
The fourth output bank (CLK4A/CLK4B) can produce the
1 32
1
QFN32
MN SUFFIX
CASE 485CE
NB3H
5150â01
AWLYYWWG
following integer and FRACâN frequencies in pinâstrap mode:
25 MHz, 33.33 MHz, 66.66 MHz, 100 MHz, 125 MHz, 133.33 MHz,
156.25 MHz or 161.1328 MHz.
Each output block can create two singleâended inâphase LVCMOS
outputs or one differential pair of LVPECL outputs.
Each of the four output blocks is independently powered by a
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= PbâFree Package
separate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V for
LVCMOS.
The serial (I2C and SMBUS) interface can be used with register files
*For additional marking information, refer to
Application Note AND8002/D.
to program a variety of functions including the frequencies and output
levels of each divider block which can be individually enabled and
ORDERING INFORMATION
disabled.
See detailed ordering and shipping information on page 18 of
this data sheet.
Features
⢠Flexible Input Reference â 25 MHz Crystal, Oscillator,
⢠1 ps maximum RMS Phase Jitter FRACâN (CLK4)
SingleâEnded or Differential Clock
161.1328 MHz
⢠Four Independent UserâProgrammable Clock
⢠I2C / SMBus Compatible Interface
Frequencies from 25 MHz to 250 MHz
⢠Independently Configurable Outputs:
Up to Eight LVCMOS Single Ended outputs or,
Up to Four Differential LVPECL Outputs or any
combination of LVCMOS and LVPECL
⢠Flexible Input/Core and Output Power Supply
Combinations:
VDD (Core) = 3.3 V ±5% or 2.5 V ±5%
VDDOn (Outputs) = 3.3 V ±5% or 2.5 V ±5% or
1.8 V ±5% (LVCMOS Only)
⢠Independent Power Supply for each Output Bank
⢠300 ps max Output Rise and Fall Times, LVPECL
⢠1000 ps max Output Rise and Fall Times, LVCMOS
⢠300 fs maximum RMS Phase Jitter IntergerâN
(CLK1:4) 156.25 MHz
⢠â40°C to +85°C Ambient Operating Temperature
⢠Zero ppm Multiplication Error
⢠Fractional Divide Ratios for Implementing Arbitrary
FEC/InverseâFEC Ratios
⢠For Additional Frequency and Output Type
Combinations, Contact ON Semiconductor Sales Office
⢠32âPin QFN, 5 mm x 5 mm
⢠This is a PbâFree Device
Applications
⢠Telecom
⢠Networking
⢠Ethernet
⢠SONET
© Semiconductor Components Industries, LLC, 2015
1
October, 2015 â Rev. 0
Publication Order Number:
NB3H5150â01/D
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