N01L63W3A Datasheet, PDF (5/10 Pages) ON Semiconductor – 1Mb Ultra-Low Power Asynchronous CMOS SRAM 64K × 16 bit

N01L63W3A
Timing Test Conditions
Item
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
Operating Temperature
0.1V_CC to 0.9 V_CC
5ns
0.5 V_CC
CL = 30pF
-40 to +85 ^oC
Timing
Item
Read Cycle Time
Address Access Time
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
Address Setup Time
Write Recovery Time
Write to High-Z Output
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
Symbol
t_RC
t_AA
t_CO
t_OE
t_LB, t_UB
t_LZ
t_OLZ
t_LBZ, t_UBZ
t_HZ
t_OHZ
t_LBHZ, t_UBHZ
t_OH
t_WC
t_CW
t_AW
t_LBW, t_UBW
t_WP
t_AS
t_WR
t_WHZ
t_DW
t_DH
t_OW
2.3 - 3.6 V
Min.
Max.
70
70
70
35
35
10
5
10
0
20
0
20
0
20
10
70
50
50
50
40
0
0
20
40
0
5
2.7 - 3.6 V
Min.
Max.
55
55
55
30
30
10
5
10
0
20
0
20
0
20
10
55
40
40
40
40
0
0
20
35
0
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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