N01L63W3A Datasheet, PDF (2/10 Pages) ON Semiconductor – 1Mb Ultra-Low Power Asynchronous CMOS SRAM 64K × 16 bit

N01L63W3A
Functional Block Diagram
Address
Inputs
A0 - A3
Word
Address
Decode
Logic
Address
Inputs
A4 - A15
Page
Address
Decode
Logic
CE
WE
OE
Control
UB
Logic
LB
4K Page
x 16 word
x 16 bit
RAM Array
Input/
Output
Mux
and
Buffers
I/O0 - I/O7
I/O8 - I/O15
Functional Description
CE
WE OE
UB
LB
I/O₀ - I/O₁₅₁
MODE
POWER
H
X
X
X
X
L
X
X
H
H
L
L
X³
L¹
L¹
L
H
L
L¹
L¹
L
H
H
L¹
L¹
High Z
High Z
Data In
Data Out
High Z
Standby²
Active
Write³
Read
Active
Standby
Active
Active
Active
Active
1. When UB and LB are in select mode (low), I/O₀ - I/O₁₅ are affected as shown. When LB only is in the select mode only I/O₀ - I/O₇
are affected as shown. When UB is in the select mode only I/O₈ - I/O₁₅ are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance¹
Item
Symbol
Test Condition
Input Capacitance
I/O Capacitance
C_IN
V_IN = 0V, f = 1 MHz, T_A = 25^oC
C_I/O
V_IN = 0V, f = 1 MHz, T_A = 25^oC
1. These parameters are verified in device characterization and are not 100% tested
Min Max Unit
8
pF
8
pF
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