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MC74HC165A_05 Datasheet, PDF (5/12 Pages) ON Semiconductor – 8−Bit Serial or Parallel−Input/ Serial−Output Shift Register High−Performance Silicon−Gate CMOS | |||
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MC74HC165A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Symbol
Parameter
VCC
Guaranteed Limit
V â 55 to 25_C v 85_C v 125_C Unit
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tsu Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load 2.0
75
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ (Figure 4)
3.0
30
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ 4.5
15
6.0
13
95
110
ns
40
55
19
22
16
19
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tsu Minimum Setup Time, Input SA to Clock (or Clock Inhibit)
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ (Figure 5)
2.0
75
3.0
30
4.5
15
6.0
13
95
110
ns
40
55
19
22
16
19
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tsu Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit) 2.0
75
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ (Figure 6)
3.0
30
4.5
15
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ 6.0
13
95
110
ns
40
55
19
22
16
19
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tsu Minimum Setup Time, Clock to Clock Inhibit
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ (Figure 7)
2.0
75
3.0
30
4.5
15
6.0
13
95
110
ns
40
55
19
22
16
19
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ th
Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs 2.0
5
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ (Figure 4)
3.0
5
4.5
5
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ 6.0
5
5
5
ns
5
5
5
5
5
5
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ th
Minimum Hold Time, Clock (or Clock Inhibit) to Input SA
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ (Figure 5)
2.0
5
3.0
5
4.5
5
6.0
5
5
5
ns
5
5
5
5
5
5
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ th
Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load
2.0
5
(Figure 6)
3.0
5
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ 4.5
5
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ 6.0
5
5
5
ns
5
5
5
5
5
5
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ trec Minimum Recovery Time, Clock to Clock Inhibit
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ (Figure 7)
2.0
75
3.0
30
4.5
15
6.0
13
95
110
ns
40
55
19
22
16
19
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tw Minimum Pulse Width, Clock (or Clock Inhibit)
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ (Figure 1)
2.0
70
3.0
27
4.5
15
6.0
13
90
100
ns
32
36
19
22
16
19
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tw Minimum Pulse width, Serial Shift/Parallel Load
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ (Figure 2)
2.0
70
3.0
27
4.5
15
6.0
13
90
100
ns
32
36
19
22
16
19
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tr, tf Maximum Input Rise and Fall Times
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ (Figure 1)
2.0
1000
3.0
800
4.5
500
6.0
400
1000
1000
ns
800
800
500
500
400
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighâSpeed CMOS Data Book
(DL129/D).
http://onsemi.com
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