MC74HC112A Datasheet, PDF (5/8 Pages) ON Semiconductor – Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS

MC74HC112A
SWITCHING WAVEFORMS
t_f
t_r
90%
V_CC
CLOCK
50%
10%
GND
t_w
1/f_max
t_PLH
t_PHL
90%
Q or Q 50%
10%
t_TLH
t_THL
Figure 1.
t_w
V_CC
SET OR
50%
RESET
GND
t_PHL
Q OR Q
50%
t_PLH
Q OR Q
50%
t_rec
CLOCK
V_CC
50%
GND
Figure 2.
VALID
V_CC
J OR K
50%
GND
t_su
t_h
V_CC
CLOCK
50%
GND
Figure 3.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
RESET ^{15, 14}
J ^{3, 11}
K ^2,12
CL
1, 13
CLOCK
SET ^{4, 10}
EXPANDED LOGIC DIAGRAM
CL
CL
CL
CL
CL
CL
CL
CL
CL
5, 9
Q
CL
CL
6, 7
Q
CL
CL
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