MC74HC112A Datasheet, PDF (2/8 Pages) ON Semiconductor – Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS

MC74HC112A
CLOCK 1 1
K1 2
J1 ₃
SET 1 4
Q1 ₅
Q1 6
Q2 7
GND 8
16 V_CC
15 RESET 1
14 RESET 2
13 CLOCK 2
12 K2
11 J2
10 SET 2
9 Q2
Figure 1. Pin Assignment
FUNCTION TABLE
Inputs
Set Reset Clock J K
Outputs
QQ
L
H
XXX
HL
H
L
XXX
LH
L
L
XXX
L* L*
HH
L L No Change
HH
LH
LH
HH
HL
HL
HH
HH
Toggle
HH
L X X No Change
H
H
H X X No Change
HH
X X No Change
*Both outputs will remain low as long as Set and
Reset are low, but the output states are unpre-
dictable if Set and Reset go high simultaneously.
SET 1 ⁴
K1 ²
CLOCK 1 ¹
J1 ³
RESET 1 ¹⁵
5 _Q1
6 _Q1
SET 2 ¹⁰
K2 ¹²
CLOCK 2 ¹³
J2 ¹¹
RESET 2 ¹⁴
9 _Q2
7 _Q2
PIN 16 = V_CC
PIN 8 = GND
Figure 2. Logic Diagram
ORDERING INFORMATION
Device
Package
Shipping^†
MC74HC112ANG
PDIP−16
(Pb−Free)
500 Units / Rail
MC74HC112ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC112ADR2G
SOIC−16
(Pb−Free)
2500 Units / Reel
MC74HC112ADTR2G
TSSOP−16*
2500 Units / Reel
MC74HC112AFELG
SOEIAJ−16
(Pb−Free)
2000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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