MC74HC03A_06 Datasheet, PDF (5/9 Pages) ON Semiconductor – Quad 2−Input NAND Gate with Open−Drain Outputs High−Performance Silicon−Gate CMOS

INPUT A
OUTPUT Y
MC74HC03A
t_r
t_f
90%
50%
10%
t_PZL t_PLZ
90%
50%
10%
10%
t_THL
Figure 1. Switching Waveforms
V_CC
GND
HIGH
IMPEDANCE
V_OL
V_CC
DEVICE
UNDER
TEST
1kW
OUTPUT
R_pd
TEST
POINT
C_L*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
25
TYPICAL
T=25°C
20
V_CC=5V
T=25°C
15
T=85°C
10
T=125°C
EXPECTED MINIMUM*
5
0
0
1
2
3
4
5
V_O, OUTPUT VOLTAGE (VOLTS)
*The expected minimum curves are not guarantees, but are design aids.
Figure 3. Open−Drain Output Characteristics
V_CC
A1
1/4
Y1
B1
HC03
A2
1/4
Y2
B2
HC03
PULLUP
RESISTOR
OUTPUT
An
1/4
Yn
Bn
HC03
OUTPUT = Y1 • Y2 • . . . • Yn
= A1B1 • A2B2 • . . . • AnBn
Figure 4. Wired AND
LED1
LED2
LED
ENABLE
V_CC
+
V_R
−
+
V_F
−
1/4
HC03
V_CC
1/4
HC03
DESIGN EXAMPLE
CONDITIONS: I_D^10mA
TYPICAL CURVE, at I_D=10mA,
V_DS^0.4V
NR
+
VCC
* VF
ID
*
VO
+
5V
*
1.7V *
10mA
0.4V
+ 290W
USE R = 270W
Figure 5. LED Driver With Blanking
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