MC74HC03A_06 Datasheet, PDF (4/9 Pages) ON Semiconductor – Quad 2−Input NAND Gate with Open−Drain Outputs High−Performance Silicon−Gate CMOS

MC74HC03A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
V_CC
Guaranteed Limit
V −55 to 25°C ≤85°C ≤125°C Unit
V_IH
Minimum High−Level Input Voltage V_out = 0.1V or V_CC −0.1V
|I_out| ≤ 20mA
2.0
1.50
1.50 1.50
V
3.0
2.10
2.10 2.10
4.5
3.15
3.15 3.15
6.0
4.20
4.20 4.20
V_IL
Maximum Low−Level Input Voltage V_out = 0.1V or V_CC − 0.1V
|I_out| ≤ 20mA
2.0
0.50
0.50 0.50
V
3.0
0.90
0.90 0.90
4.5
1.35
1.35 1.35
6.0
1.80
1.80 1.80
V_OL
Maximum Low−Level Output
Voltage
V_out = 0.1V or V_CC − 0.1V
|I_out| ≤ 20mA
2.0
0.1
4.5
0.1
6.0
0.1
0.1
0.1
V
0.1
0.1
0.1
0.1
V_in = V_IH or V_IL
|I_out| ≤ 2.4mA 3.0
|I_out| ≤ 4.0mA 4.5
|I_out| ≤ 5.2mA 6.0
0.26
0.26
0.26
0.33 0.40
0.33 0.40
0.33 0.40
I_in
Maximum Input Leakage Current
V_in = V_CC or GND
6.0
±0.1
±1.0
±1.0
mA
I_CC
Maximum Quiescent Supply
Current (per Package)
V_in = V_CC or GND
I_out = 0mA
6.0
1.0
10
40
mA
I_OZ
Maximum Three−State Leakage
Current
Output in High−Impedance State 6.0
V_in = V_IL or V_IH
V_out = V_CC or GND
±0.5
±5.0
±10
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (C_L = 50pF, Input t_r = t_f = 6ns)
Symbol
Parameter
Guaranteed Limit
V_CC
V −55 to 25°C ≤85°C ≤125°C Unit
t_PLZ,
t_PZL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
120
3.0
45
4.5
24
6.0
20
150
180
ns
60
75
30
36
26
31
t_TLH,
t_THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
75
3.0
27
4.5
15
6.0
13
95
110
ns
32
36
19
22
16
19
C_in
Maximum Input Capacitance
10
10
10
pF
C_out
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V_CC = 5.0 V, V_EE = 0 V
C_PD
Power Dissipation Capacitance (Per Buffer)*
8.0
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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