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CS1087 Datasheet, PDF (5/12 Pages) ON Semiconductor – Vacuum Fluorescent Display Tube Driver
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CS1087
GRID1 GRID2 GRID3 AN1 AN2 AN3
VBB
GND
POR
VREG
VREG
AN23 AN24 AN25 AN26 AN27 AN28 AN29
GREN
VREG
STB
VREG
DIN
VREG
CLK
VREG
METAL MASK ROM
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
LE
VREG
DQ
CLK
R
DOUT
Output Drive Capability
Grid Outputs: 50 mA
AN24–AN29: 20 mA
AN1–AN23: 2.0 mA
Figure 2. Block Diagram
OPERATION DESCRIPTION
Upon the initial application of power, the power on reset
function will cause all of the anode and grid driver outputs
to be off and all shift register outputs to be set low. Data is
fed into the shift register through the DIN pin at the rising
edge of the CLK input. Thirty two bits of data are capable of
being stored by the shift register. Once the desired pattern is
stored in the shift register, it can be transferred to the latch
by setting the STB input high. The output of each latch
drives its corresponding output stage. A logic high input to
the shift register/latch will cause the corresponding output
to turn on. A logic low input to the shift register/latch will
cause the corresponding output to turn off. Please note that
if the STB is held high, the outputs of the latch reflect the
outputs of the corresponding shift register bits and will
change if data is shifted in.
The three GRID outputs are gated by the GREN input.
When GREN is low, the GRID outputs are forced low
regardless of the state of the corresponding latch output.
When GREN is high, the GRID outputs correspond to the
state of their respective latch outputs. The anode outputs,
AN1 to AN29 are always enabled.
The DOUT pin is the output of the last stage of the shift
register to allow serial cascading of this IC with other
devices. Data from the last stage of the shift register is
supplied to the DOUT pin delayed by 1/2 CLK cycle. Data on
the DOUT output changes with the falling edges of the CLK
to prevent logic race conditions between the CLK and the
DIN of the next IC in the serial chain.
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