CAT93C66_15 Datasheet, PDF (5/13 Pages) ON Semiconductor – 4 kb Microwire Serial CMOS EEPROM

CAT93C66, CAT93W66
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C66,
CAT93W66 will come out of the high impedance state and,
after sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable after
the specified time delay (t_PD0 or t_PD1).
For the CAT93C66, CAT93W66 after the initial data word
has been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 3.
Erase/Write Enable and Disable
The device powers up in the write disable state. Any
writing after power−up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C66,
CAT93W66 write and erase instructions, and will prevent
any accidental writing or clearing of the device. Data can be
read normally from the device regardless of the write
enable/disable status. The EWEN and EWDS instructions
timing is shown in Figure 4.
t_SKHI
t_SKLOW
t_CSH
SK
t_DIS
DI
VALID
t_CSS
CS
t_DIH
VALID
t_DIS
t_PD0, t_PD1
t_CSMIN
DO
DATA VALID
Figure 2. Synchronous Data Timing
SK
CS
A_N A_N−1
A₀
DI
11 0
t_PD0
HIGH−Z
DO
Don’t Care
Dummy 0
D_{15 . . .} D₀
or
D_{7 . . .} D₀
Address + 1
D_{15 . . .} D₀
or
D_{7 . . .} D₀
Address + 2
D_{15 . . .} D₀
or
D_{7 . . .} D₀
Address + n
D_{15 . . .}
or
D_{7 . . .}
Figure 3. READ Instruction Timing
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