CAT5241_13 Datasheet, PDF (5/16 Pages) ON Semiconductor – Quad Digital Potentiometer (POT)

CAT5241
Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
I_CC
Power Supply Current
f_SCL = 400 kHz
1
I_SB
Standby Current (V_CC = 5.0 V)
V_IN = GND or V_CC;
1
SDA = GND;
RWX = GND (Note 8)
I_LI
Input Leakage Current
V_IN = GND to V_CC
I_LO
Output Leakage Current
V_OUT = GND to V_CC
V_IL
Input Low Voltage
V_IH
Input High Voltage
V_OL1
Output Low Voltage (V_CC = 3.0 V)
I_OL = 3 mA
8. All four wiper terminals RW0, RW1, RW2, and RW3 are tied to ground.
−1
V_CC x 0.7
10
10
V_CC x 0.3
V_CC + 1.0
0.4
Table 6. CAPACITANCE (Note 9) (T_A = 25C, f = 1.0 MHz, V_CC = +5.0 V)
Symbol
Parameter
Test Conditions
Min
Typ
Max
C_I/O
Input/Output Capacitance (SDA)
V_I/O = 0 V
8
C_IN
Input Capacitance (A0, A1, A2, A3, SCL)
V_IN = 0 V
6
Units
mA
mA
mA
mA
V
V
V
Units
pF
pF
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
f_SCL
Clock Frequency
T_I (Note 9)
Noise Suppression Time Constant at SCL, SDA Inputs
t_AA
SLC Low to SDA Data Out and ACK Out
t_BUF (Note 9)
Time the Bus Must Be Free Before a New Transmission Can Start
1.2
t_HD:STA
Start Condition Hold Time
0.6
t_LOW
Clock Low Period
1.2
t_HIGH
Clock High Period
0.6
t_SU:STA
Start Condition Setup Time (For a Repeated Start Condition)
0.6
t_HD:DAT
Data in Hold Time
0
t_SU:DAT
Data in Setup Time
100
t_R (Note 9)
SDA and SCL Rise Time
t_F (Note 9)
SDA and SCL Fall Time
t_SU:STO
Stop Condition Setup Time
0.6
t_DH
Data Out Hold Time
50
Max
Units
400
kHz
50
ns
0.9
ms
ms
ms
ms
ms
ms
ns
ns
0.3
ms
300
ns
ms
ns
Table 8. POWER UP TIMING (Note 9) (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
t_PUR
Power-up to Read Operation
t_PUW
Power-up to Write Operation
9. This parameter is tested initially and after a design or process change that affects the parameter.
Max
Units
1
ms
1
ms
Table 9. WRITE CYCLE LIMITS (Note 10) (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
Max
Units
t_WR
Write Cycle Time
5
ms
10. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
http://onsemi.com
5