CAT5241_13 Datasheet, PDF (3/16 Pages) ON Semiconductor – Quad Digital Potentiometer (POT)

CAT5241
R_H0 R_H1 R_H2 R_H3
SCL
SDA
A0
A1
A2
A3
I²C BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R_W0
R_W1
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R_W2
R_W3
R_L0 R_L1 R_L2 R_L3
Figure 1. Functional Diagram
Table 1. PIN DESCRIPTION
Pin (SOIC) Name
Function
1
R_W0 Wiper Terminal for Potentiometer 0
2
R_L0 Low Reference Terminal for
Potentiometer 0
3
R_H0 High Reference Terminal for
Potentiometer 0
4
A0 Device Address, LSB
5
A2 Device Address
6
R_W1 Wiper Terminal for Potentiometer 1
7
R_L1 Low Reference Terminal for
Potentiometer 1
8
R_H1 High Reference Terminal for
Potentiometer 1
9
SDA Serial Data Input/Output
10
GND Ground
11
R_H2 High Reference Terminal for
Potentiometer 2
12
R_L2 Low Reference Terminal for
Potentiometer 2
13
R_W2 Wiper Terminal for Potentiometer 2
14
SCL Bus Serial Clock
15
A3 Device Address
16
A1 Device Address
17
R_H3 High Reference Terminal for
Potentiometer 3
18
R_L3 Low Reference Terminal for
Potentiometer 3
19
R_W3 Wiper Terminal for Potentiometer 3
20
V_CC Supply Voltage
Pin Descriptions
SCL: Serial Clock
The CAT5241 serial clock input pin is used to clock all
data transfers into or out of the device.
SDA: Serial Data
The CAT5241 bidirectional serial data pin is used to
transfer data into and out of the device. The SDA pin is an
open drain output and can be wire-OR’d with the other open
drain or open collector outputs.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of sixteen devices can be addressed
on a single bus. A match in the slave address must be made
with the address input in order to initiate communication
with the CAT5241.
R_H, R_L: Resistor End Points
The four sets of R_H and R_L pins are equivalent to the
terminal connections on a mechanical potentiometer.
R_W: Wiper
The four R_W pins are equivalent to the wiper terminal of
a mechanical potentiometer.
Device Operation
The CAT5241 is four resistor arrays integrated with I²C
serial interface logic, four 6-bit wiper control registers and
sixteen 6-bit, non-volatile memory data registers. Each
resistor array contains 63 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (R_H and R_L). R_H and R_L are symmetrical and
may be interchanged. The tap positions between and at the
ends of the series resistors are connected to the output wiper
terminals (R_W) by a CMOS transistor switch. Only one tap
point for each potentiometer is connected to its wiper
terminal at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control registers or the non-volatile memory data registers
via the I²C bus. Additional instructions allow data to be
transferred between the wiper control registers and each
respective potentiometer’s non-volatile data registers. Also,
the device can be instructed to operate in an
“increment/decrement” mode.
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