CAT28C257 Datasheet, PDF (5/13 Pages) Catalyst Semiconductor – 256K-Bit CMOS PARALLEL E2PROM

CAT28C257
Table 8. A.C. CHARACTERISTICS, WRITE CYCLE (V_CC = 5 V ±10%, unless otherwise specified.)
28C257−12
28C257−15
Symbol
Parameter
Min
Typ
Max
Min
Typ
Max
Units
t_WC
Write Cycle Time
5
5
ms
t_AS
Address Setup Time
0
0
ns
t_AH
Address Hold Time
50
50
ns
t_CS
CE Setup Time
0
0
ns
t_CH
CE Hold Time
0
0
ns
t_CW (Note 10)
CE Pulse Time
100
100
ns
t_OES
OE Setup Time
0
0
ns
t_OEH
OE Hold Time
0
0
ns
t_WP (Note 10)
WE Pulse Width
100
100
ns
t_DS
Data Setup Time
50
50
ns
t_DH
Data Hold Time
0
0
ns
t_INIT (Note 11)
Write Inhibit Period After Power−up
5
10
5
10
ms
t_BLC (Notes 11, 12) Byte Load Cycle Time
0.1
100
0.1
100
ms
10. A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration t_BLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within t_BLC max. stops the timer.
V_CC − 0.3 V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Input/Output Waveform (Note 13)
13. Input rise and fall times (10% and 90%) < 10 ns.
1.3 V
1N914
DEVICE
UNDER
TEST
3.3 K
C_L = 100 pF
OUT
C_L INCLUDES JIG CAPACITANCE
Figure 3. A.C. Testing Load Circuit (example)
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