ASM5P2304A Datasheet, PDF (5/8 Pages) Alliance Semiconductor Corporation – 3.3 V Zero Delay Buffer

ASM5P2304A
Table 6. SWITCHING CHARACTERISTICS (Notes 5, 6)
Parameter
Test Conditions
Min
Output Frequency
30 pF load
(−1, −1H) devices
10
15 pF load
(−2, −2H) devices
12
(−1, −1H) devices
10
(−2, −2H) devices
12
Duty Cycle (Note 7)
(−1, −2, −1H, −2H)
Duty Cycle (Note 7)
(−1, −2,−1H, −2H)
Output Rise Time (Note 7)
(−1, −2)
Measured at 1.4 V,
40
F_OUT < 66.66 MHz, 30 pF load
Measured at 1.4 V,
45
F_OUT ≤ 50 MHz, 15 pF load
Measured between 0.8 V
and 2.0 V, 30 pF load
Commercial temp.
Industrial temp.
Output Rise Time (Note 7)
(−1H, −2H)
Measured between 0.8 V
and 2.0 V, 30 pF load
Commercial temp.,
Industrial temp.
Output Rise Time (Note 7)
(−1, −2)
Measured between 0.8 V
and 2.0 V, 15 pF load
Output Fall Time (Note 7)
(−1, −2)
Output Fall Time (Note 7)
(−1H, −2H)
Measured between 2.0 V
and 0.8 V, 30 pF load
Measured between 2.0 V
and 0.8 V, 30 pF load
Commercial temp.
Industrial temp.
Commercial temp.,
Industrial temp.
Output Fall Time (Note 7)
(−1, −2)
Measured between 2.0 V
and 0.8 V, 15 pF load
Output−to−output skew on same bank
(−1, −1H, −2, −2H) (Note 7)
All outputs equally loaded
Output bank A −to− output bank B
skew (−1, −1H)
All outputs equally loaded
Output bank A to output Bank B
skew (−2, −2H) (Note 7)
All outputs equally loaded
Delay, REF Rising Edge to FBK
Rising Edge (Note 7)
Measured at V_DD /2
Device−to−Device Skew (Note 7)
Cycle−to−Cycle Jitter
(Note 7)
(−1, −1H)
Measured at V_DD/2 on the FBK pins of the device
Measured at 66.67 MHz, loaded outputs, 15 pF load
Measured at 66.67 MHz, loaded outputs, 30 pF load
(−2, −2H)
Measured at 133 MHz, loaded outputs, 15 pF load
Measured at 66.67 MHz, loaded outputs, 15 pF load
Measured at 66.67 MHz, loaded outputs, 30 pF load
PLL Lock Time (Note 7)
Stable power supply, valid clock presented on
REF and FBK pins
5. For all measurements use Test Circuit #1.
6. All parameters are specified at Commercial and Industrial temperature unless stated otherwise.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Typ
Max Unit
100 MHz
100
133
133
50
60
%
50
55
%
2.2
nS
2.5
1.5
2
nS
1.5
nS
2.2
nS
2.5
1.25
1.5
nS
1.5
nS
200
pS
200
400
0
±250 pS
0
500
pS
180
pS
200
125
380
400
1.0
mS
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