82V3012 Datasheet, PDF (5/32 Pages) Integrated Device Technology – T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

LIST OF FIGURES
Figure - 1
Figure - 2
Figure - 3
Figure - 4
Figure - 5
Figure - 6
Figure - 7
Figure - 8
Figure - 9
Figure - 10
Figure - 11
Figure - 12
Figure - 13
Figure - 14
Figure - 15
IDT82V3012 SSOP56 Package Pin Assignment ................................................................................................................................ 2
State Control Circuit .......................................................................................................................................................................... 10
State Control Diagram....................................................................................................................................................................... 10
TIE Control Block Diagram................................................................................................................................................................ 12
Reference Switch with TIE Control Block Enabled............................................................................................................................ 13
Reference Switch with TIE Control Block Disabled........................................................................................................................... 13
DPLL Block Diagram ......................................................................................................................................................................... 14
Clock Oscillator Circuit ...................................................................................................................................................................... 15
Power-Up Reset Circuit..................................................................................................................................................................... 16
IDT82V3012 Power Decoupling Scheme.......................................................................................................................................... 16
Timing Parameter Measurement Voltage Levels .............................................................................................................................. 27
Input to Output Timing (Normal Mode).............................................................................................................................................. 29
Output Timing 1................................................................................................................................................................................. 30
Output Timing 2................................................................................................................................................................................. 31
Input Control Setup and Hold Timing ................................................................................................................................................ 31
List of Figures
5
February 6, 2009