82V3012 Datasheet, PDF (12/32 Pages) Integrated Device Technology – T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

IDT82V3012
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Table - 4. The selected reference signal is sent to the TIE control block,
Reference Input Monitor and Invalid Input Signal Detection block for
further processing.
Table - 4 Input Reference Selection
IN_sel
Input Reference
0
Fref0
1
Fref1
When a transient voltage occurs on the IN_sel pin, the operating
mode will be changed to Short Time Holdover (S4) with the TIE Control
Block automatically disabled. At the stage of S4, if no IN_sel transient
occurs, the reference signal will be switched from one to the other, and
the operating mode will be changed back to Normal (S1) automatically.
During the change from S4 to S1, the TIE Control Block can be enabled
or disabled, depending on the logic level on the TIE_en pin. See Figure -
3 for details.
2.4
REFERENCE INPUT MONITOR
The Telcordia GR-1244-CORE standard recommends that the DPLL
should be able to reject the references that are off the nominal frequency
by more than ±12 ppm. The IDT82V3012 monitors the Fref0 and Fref1
frequencies and outputs two signals at MON_out0 pin and MON_out1
pin to indicate the monitoring results respectively. Whenever the Fref0
frequency is off the nominal frequency by more than ±12 ppm, the
MON_out0 pin will go high. The MON_out1 pin indicates the monitoring
result of Fref1 in the same way. The MON_out0 and MON_out1 signals
are updated every 2 seconds.
2.5
INVALID INPUT SIGNAL DETECTION
This circuit is used to detect if the selected input reference (Fref0 or
Fref1) is out of the capture range. Refer to “3.6 Capture Range” for
details. This includes a complete loss of the input reference and a large
frequency shift in the input reference.
If the input reference is invalid (out of the capture range), the
IDT82V3012 will be automatically changed to the Holdover mode (Auto-
Holdover). When the input reference becomes valid, the device will be
changed back to the Normal mode and the output signals will be locked
to the input reference.
In the Holdover mode, the output signals are based on the output
reference signal 30 ms to 60 ms prior to entering the Holdover mode.
The amount of phase drift while in holdover can be negligible because
the Holdover mode is very accurate (e.g., 0.025 ppm). Consequently,
the phase delay between the input and output after switching back to the
Normal mode is preserved.
2.6
TIE CONTROL BLOCK
If the current reference is badly damaged or lost, it is necessary to
use the other reference or the one generated by storage techniques
instead. But when switching the reference, a step change in phase on
the input reference will occur. A step change in phase in the input to
DPLL may lead to an unacceptable phase change on the output signals.
The TIE control block, when enabled, prevents a step change in phase
on the input reference signals from causing a step change in phase on
the output of the DPLL block. Figure - 4 shows the TIE Control Block
diagram.
TIE_en
Step Generation
IN_sel
Fref0
Fref1
Fref
Reference
Select Circuit
Measure
Circuit
Storage
Circuit
Trigger
Circuit
Virtual
Reference
Signal
Feedback
Signal
TCLR
Figure - 4 TIE Control Block Diagram
When the TIE Control Block is enabled manually or automatically (by
the TIE_en pin or TIE auto-enable logic generated by the State Control
Circuit), it works under the control of the Step Generation circuit.
At the Measure Circuit stage, the selected reference signal (Fref0 or
Fref1) is compared with the feedback signal (current output feed back
from the Frequency Select Circuit). The phase difference between the
input reference and the feedback signal is stored in the Storage Circuit
for TIE correction. According to the value stored in the storage circuit,
the Trigger Circuit generates a virtual reference with the same phase as
the previous reference. In this way, the reference can be switched
without generating a step change in phase.
Figure - 5 shows the phase transient that will result if a reference
switch is performed with the TIE Control Block enabled.
The value of the phase difference in the Storage Circuit can be
cleared by applying a logic low reset signal to the TCLR pin. The
minimum width of the reset pulse should be 300 ns.
When the IDT82V3012 primarily enters the Holdover mode for a
short time period and then returns back to the Normal mode, the TIE
Control Circuit should not be enabled. This will prevent undesired
accumulated phase change between the input and output.
If the TIE Control Block is disabled manually or automatically, a
reference switch will result in a phase alignment between the input
signal and the output signal as shown in Figure - 6. The slope of the
phase adjustment is limited to 5 ns per 125 µs.
Functional Description
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February 6, 2009