STD5407N Datasheet, PDF (4/6 Pages) ON Semiconductor – 40 V, 38 A, Single N-Channel, DPAK

NTD5407N, STD5407N
TYPICAL PERFORMANCE CURVES
1800
V_DS = 0 V V_GS = 0 V
C_iss
1200
C_rss
600
15
T_J = 25°C
12
9
C_iss
6 ^QGS
QT
V_DS
Q_GD
35
28
V_GS
21
14
C_oss
3
0
C_rss
0
10 5
0
5 10 15 20 25 30
0
V_GS V_DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
7
I_D = 36 A
T_J = 25°C
0
5
10
15
20
Q_G, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and
Drain−To−Source Voltage vs. Total Charge
1000
V_DS = 32 V
I_D = 38 A
V_GS = 10 V
100
10
t_d(off)
t_f
t_r
t_d(on)
1
1
10
100
R_G, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
15
14 V_GS = 0 V
13 T_J = 25°C
12
11
10
9
8
7
6
5
4
3
2
1
0
0.3
0.6
0.9
1.2
V_SD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
1000
100
V_GS = 10 V
SINGLE PULSE
T_C = 25°C
10 ms
100 ms
10
1 ms
10 ms
1
dc
R_DS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
100
V_DS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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