PACVGA105_11 Datasheet, PDF (4/6 Pages) ON Semiconductor – VGA Port Companion Circuit

PACVGA105
SPECIFICATIONS (Cont’d)
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Conditions
Min
Typ
Max Units
V_F
Diode Forward Voltage
V_OH Logic High Output Voltage
V_OL Logic Low Output Voltage
I_IN
Input Current
R, G and B Pins
HSYNC, VSYNC Pins
HSYNC, VSYNC Pins
I_CC
V_CC Supply Current
I_F = 10 mA
I_OH = −4 mA, V_CC = 4.5 V
I_OL = 4 mA, V_CC = 4.5 V
V_RGB = 3.63 V, V_IN = V_RGB or GND
V_AUX = 3.63 V, V_IN = V_AUX
V_AUX = 3.63 V, V_IN = GND
V_CC = 5.5 V, V_AUX = V_RGB = 2.97 V,
All Inputs and Outputs Floating
1.0
V
4.0
V
0.4
V
mA
1
1
−30.0 −72.5 −95.0
35
100
mA
I_RGB V_RGB Supply Current
R, G and B Pins at V_CC or GND,
All Inputs and Outputs Floating
10
mA
C_IN
Input Capacitance
R, G and B pins
HSYNC, VSYNC pins
DDC_DATA, DDC_CLK pins
Note 2 Applies for All Cases
pF
5
10
5
R_PU Pull−up Resistance
DDC_DATA, DDC_CLK pins
1.62 1.80 1.98
kW
V_ESD ESD Withstand Voltage
V_CC = 5 V, V_RGB = 3.3 V, V_AUX = 3.3 V
8
kV
(Note 3)
t_PLH
SYNC Buffer L  H
Propagation Delay
C_L = 50 pF, V_CC = 5.0 V, R_L = 500 W
(Note 4)
7.0
15.0
ns
t_PHL
SYNC Buffer H  L
Propagation Delay
C_L = 50 pF, V_CC = 5.0 V, R_L = 500 W
(Note 4)
7.0
15.0
ns
t_R, t_F SYNC Buffer Output Rise & Fall Times
C_L = 50 pF, V_CC = 5.0 V, R_L = 500 W
(Note 4)
7.0
ns
1. All parameters specified over standard operating conditions unless otherwise noted.
2. Measured at 1 MHz. R/G/B inputs biased at 1.65 V with V_RGB = 3.3 V. DDC_CLK and DDC_DATA biased at 2.5 V with V_CC = 5 V. HSYNC
and VSYNC inputs biased at V_AUX or GND with V_AUX = 3.3 V and V_CC = 5 V.
3. Per the IEC−61000−4−2 International ESD Standard, Level 4 contact discharge method. V_RGB and V_CC must be bypassed to GND via a low
impedance ground plane with a 0.2 mF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the
applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: R, G, B, HSYNC_OUT,
VSYNC_OUT, DDC_CLK and DDC_DATA. The HSYNC and VSYNC inputs are ESD protected to the industry standard 2 kV per the Human
Body Model (MIL−STD−883, Method 3015).
4. Applicable to the SYNC buffers only. Input signals swing between 0 V and 3.0 V, with rise and fall times  5 ns. Guaranteed by correlation
to buffer output drive currents.
http://onsemi.com
4